QuickLogic Corporation

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everyone to QuickLogix Corporation's second quarter fiscal 2025 earnings results conference call. As a reminder, today's call is being recorded for replay purposes through August 19, 2025. I would now like to turn the conference over to Ms. Alison Ziegler of Darrow's Associates. Ms. Ziegler, please go ahead.

Thank you, Operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited to statements regarding our future profitability and cash flows, expectations regarding our future business, and statements regarding the timing, milestones, and payments related to our government contracts, and statements regarding our ability to successfully exit sense amounts. Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time-to-market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, national disasters, and other business interruptions that could disrupt supply or delivery of or demand for company's products and changes in tax rates and exposure to additional tax liability. For more detailed discussions on the risks, uncertainties, and assumptions that could result in these differences, please refer to the risk factors discussed in QuickLogic's most recently fired periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR webpage that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under regulation . A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR webpage shortly after the conclusion of today's earnings call. I'd now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison, and good afternoon. Since our last conference call, we have focused considerable engineering resources towards two strategic initiatives that we will discuss today. We strongly believe these initiatives will accelerate storefront design wins for our strategic Rathart FPGA and expand our served available market to include very high density EFPGA hard IP designs targeting advanced fabrication nodes and EFPGA designs that require certain advanced capabilities. This allocation of engineering resources has pushed deliverables and associated revenue recognition forward for several contracts. This has decreased our revenue outlook for Q3, but it is expected to fuel a substantial increase in Q4 revenue. Now let's discuss what drove us to make these decisions and the opportunities we expect them to enable beginning in Q4. It has been well publicized that the DoD has prioritized certain strategic defense systems, including Golden Dome. As a result, U.S.-based defense contractors have accelerated the development of the associated programs. Many of these programs will require radiation-tolerant and, in some cases, strategic radiation-hardened semiconductor devices that are fabricated in the U.S. Due to this, we took steps to ensure we are ready to support this accelerated development. After working nights and weekends, our engineering team delivered design files on Sunday to global foundries to fabricate a strategic RadHard or SRH FPGA test chip using its 12 LP fabrication node. This initiative was financed by QuickLogic and is independent from our contract with the US government. Our decision to invest the money and resources to develop this test chip now is based on our belief that it is critical to helping us secure strategic design wins and accelerate our storefront business model. We have been discussing this initiative with certain large dibs for a couple of years who have programs in development today that are good candidates for an SRH FPGA. We have designed a test ship to meet their requirements. To ensure we are ready to leverage this opportunity, and our accelerated introduction of Astralis 2.0, which I'll discuss in a moment, we raised the money in June and early July with our established ATM. We anticipate ROI from our SRH FPGA test chip initiative beginning in 2026. And if we are successful in winning designs, we believe storefront production contracts could be worth hundreds of millions of dollars in the coming years. When we initiated our work to develop an SRH FPGA test chip, we believed certain DIBs would be ready to evaluate it in early 2026. However, during a conversation within the last week with one of the large DIBs, I was advised they would like access to the test chip as soon as possible and told me the test chip, as it is defined, may satisfy their program requirements. I know from speaking with investors at conferences and by phone that many of you are focused on the phenomenal growth potential of our storefront business model. I couldn't agree more, and I can assure you that I am intensely focused on executing the prerequisites needed to realize this objective. These include completing the first tape out that we internally funded in nearly a decade. The SRHFPJ technology we've developed is the foundation of our storefront model. And getting a 12 LP test chip in the hands of the dibs that are developing strategic defense systems today is a critical element to our success. The importance of demonstrating our SRH FPGA test chip goes well beyond the storefront designs we believe it will enable us to secure. FPGA is the number one spend category for semiconductor devices by the defense industrial base. And custom ASICs are a close second. Together, We believe these two categories make up roughly half of the DIB Semiconductor TAM. We expect many of these new strategic designs will use either discrete FPGA devices that we can store front or embedded FPGA IP we can license in new ASIC designs. By delivering a discrete SRH FPGA test chip fabricated on the 12LP process, We are demonstrating the broader capability of our EFPGA hard IP for ASIC applications that will need to either be radiation tolerant or SRH. We introduced Astralis in 2021. It is a proprietary tool that we use internally to quickly generate customer-specific EFPGA hard IP, and it provides us with a substantial competitive advantage. While we have refined Astralis through the years to enhance these advantages, the release of version 2.0 will mark its first significant update. Our success in advanced fabrication nodes, which include 12 nanometer nodes at GlobalFoundries and TSMC and Intel 18A, have led to customer contracts and engagements for very high density EFPGA IP cores that will require the advancements we are introducing with Astralis 2.0. These include an awarded 12 nanometer contract, a pending 12 nanometer contract, and a potential Intel 18A contract for a 1 million plus LUT or lookup table production design. We are also seeing customer requirements for faster core speeds, improved silicon utilization, and certain new features for high reliability applications. Astralis 2.0 will support these requirements and more. Due to these factors, we have given Astralis 2.0 a very high priority. We are confident that we will deliver our first eFPGA hard IP using Astralis 2.0 for an existing revenue generating contract during Q4. While we are also confident this will contribute to a substantial sequential increase in Q4 revenue, some of the revenue that we've pushed forward may extend into early Q1. Due to this, we are conservatively projecting a modest decrease in full year 2025 revenue relative to 2024. Astralis, including the soon to be completed version 2.0, is our proprietary hard IP generation tool that we use internally. Aurora is the development tool we provide to our customers. The two tools work hand in hand and together optimize the efficiency of the design process, hard IP generation, and the resulting PPA of the silicon implementation. PPA is an industry term meaning power, performance, and area. Aurora started out as a development platform with open source synthesis, which was fine for trailing edge fabrication nodes and low to medium density designs. However, many of the large customers we are currently engaged with prefer the Synopsys Simplify FPGA design tool. which is particularly beneficial for leading edge fabrication nodes and high density designs. To accommodate this requirement as quickly as possible, we adapted Aurora 2.9 to be compatible with Simplify and branded it Aurora Pro 2.9. We discussed this in our February conference call. Since then, we've worked closely with Synopsys to optimize Simplify for our proprietary architecture and seamlessly integrated it into Aurora Pro. This was covered in a press release issued July 28th. The integration of Simplify is tailored to QuickLogic's EFPGA architecture and includes optimizations for embedded carry chains, block RAM, and DSP blocks. This significantly reduces critical path delays and accelerates design convergence, resulting in up to a 35% improvement in maximum frequency. This integration also delivers up to a 50% improvement in resource utilization. as demonstrated by customer designs achieving over 96% LUT utilization. Now, a brief update on our U.S. government SRH FPGA contract. Q3 will mark the low point for revenue recognition this year on our U.S. government SRH FPGA contract. We completed our deliverables on schedule and recognized the associated revenue during Q2. We are now waiting on the completion of key deliverables from a subcontractor. Due to this, revenue recognition from our SRH FPGA contract will be de minimis in Q3, followed by an anticipated rebound in Q4 that is funded by the current tranche. As we previously announced, we delivered customer-specific eFPGA hard IP for a customer test chip targeting Intel 18A late last April. This test ship is moving through fabrication and we expect to have our allocation of test ships to be in hand for evaluation towards the end of Q4. We have booked a second test ship contract with this U.S.-based customer valued at $500,000 that is scheduled for delivery in Q3. In addition to this, we have also been awarded a six-figure feasibility contract for a $1 million plus LUT design that we are scheduled to complete in Q4. We anticipate this will lead to an EFPGA IP contract for a high-density chiplet design during the first half of 2026. In our May conference call, I stated that a mid-seven-figure contract with this customer targeting Intel 18A was delayed due to the timing of government funding. The customer advised us that it was awarded funding for the program but funding for the production ASIC, which is a subcomponent of the program, would not be awarded until Q4. Beyond the base of business we are rapidly building with this customer, we have multiple Intel 18A engagements with other DIBs and with commercial customers that we believe will result in significant contracts beginning in Q4. Last quarter, I mentioned that we were in early discussions with customers regarding a digital proof of concept chiplet strategy that would give them a head start in chiplet development while standards are still in a state of flux. These discussions have expanded to include two of our large strategic partners who will actively help us promote the digital proof of concept chiplet we have jointly specified directly to potential end customers as a QuickLogic storefront device. Due to the fact we can leverage our existing library for the eFPGA core in the chiplet and integrate that with readily available third-party IP, The digital proof of concept chiplet will be completed before our next conference call and will be a low cost investment with potentially very high return as a storefront device. It will be designed to target any of the advanced fabrication nodes we've discussed and can be easily modified to fit customer specific requirements. Please note this digital proof of concept chiplet initiative will not utilize engineering resources that we have dedicated to Astralis 2.0 our 12OP SRH test ship, or revenue generating hard IP contracts. Before turning the call over to Elias, I would like to take a moment to acknowledge the passing of Christine Russell, who served as a QuickLogic board director and audit committee chair for two decades. She was a dear friend and will be missed. Ron Shelton has joined as a new member of our board of directors and will assume the role of audit committee chair. Ron has served as chief financial officer for both public and private semiconductor companies for more than 25 years and is very well respected across Silicon Valley. Ron is also very well connected with investment bankers and analysts, some of whom already cover QuickLogic. We look forward to his strategic insights and guidance contributing to the company's continued growth and success. With this, I will turn the call over to Elias for financial results and outlook.