Aehr Test Systems

Greetings. Welcome to the Air Test System's Fiscal 2026 Third Quarter Financial Results Conference Call. At this time, all participants are in a listen-only mode. A question and answer session will follow the formal presentation. If anyone should require operator assistance during the conference, please press star zero on your telephone keypad. Please note, this conference is being recorded. I will now turn the conference over to your host, Jim Byers of Pondell Wilkinson Investor Relations. You may begin.

Thank you, Operator. Good afternoon and welcome to Airtest Systems' third quarter fiscal 2026 financial results conference call. With me on today's call are Airtest Systems President and Chief Executive Officer, Gane Erickson, and Chief Financial Officer, Chris Tiu. Before I turn the call over to Gane and Chris, I'd like to cover a few quick items. This afternoon, right after market closed, Airtest issued a press release announcing its third quarter fiscal 2026 results. That release is available on the company's website at air.com. This call is being broadcast live over the Internet for all interested parties, and the webcast will be archived on the investor relations page of the company's website. And I'd like to remind everyone that on today's call, management will be making forward-looking statements that are based on current information and estimates and are subject to a number of risks and uncertainties that could cause actual results to differ materially from those in the forward-looking statements. These factors are discussed in the company's most recent periodic and current reports filed with the SEC. These forward-looking statements, including guidance provided during today's call, are only valid as of this date, and Airtest Systems undertakes no obligation to update the forward-looking statements. And now with that, I'd like to turn the conference call over to Gane Erickson, President and CEO.

Thanks, Jim. Good afternoon, everyone, and welcome to our third quarter fiscal 26 earnings conference call. I'll start with an update on the key markets driving our business and strong demand we're seeing, particularly from AI and data center infrastructure. Chris will then review our financial results and we'll open up the call for questions. We're very pleased with the strong momentum in our business across multiple market segments, highlighted by more than $37 million in quarterly bookings and a book-to-bill ratio exceeding 3.5x. Our effective backlog, which includes the backlog of $38.7 million at the end of the fiscal third quarter, plus additional bookings received since the end of the quarter, is now over $50 million, a new company record. After generating approximately $20 million in bookings in our fiscal first half, we're already two and a half times that in second half bookings, and now expect to come in on the high side of the $60 to $80 million in second half bookings I mentioned last quarter. Demand continues to accelerate across both package level and wafer level burn-in, driven by increasing semiconductor complexity, power requirements, and deployment in mission-critical AI, networking, automotive, and industrial applications. As devices become more advanced, the need for comprehensive test and burn-in is becoming essential to ensure reliability and performance. This is driving growing adoption of our solutions across multiple markets. So let me start with wafer-level burn-in. During the quarter, we continue to make progress in growing our installed base and expanding to new customers with our wafer-level burn-in solutions. AI wafer-level burn-in is really hot right now, I guess pun intended. We received a $14 million follow-on production order from our lead wafer-level AI accelerator processor customer for multiple new fully automated Fox XP wafer-level burn-in systems to be used in data center training and inference applications. The order included multiple additional Fox XP wafer-level test and burn-in systems, each configured to test nine 300-millimeter wafers in parallel, along with a set of AERS proprietary Fox wafer pack full wafer contactors and a fully integrated Fox wafer pack auto-aligner with each system to enable hands-free operation and high-volume production. In addition, the order included multiple additional Fox wafer pack auto-aligners to upgrade the customer's existing installed base of Fox XP systems to full automation. AIR is the first company to successfully demonstrate and ship a wafer level burn-in solution for AI processors. Our Fox XP systems configured for very high power, high current AI processors began shipping last year and provides the highest power per wafer capability available in the market, delivering up to thousands of amperes of current per wafer. This order further expands their installed base of Fox XP systems and adds full automation across their production lines, highlighting the growing importance of wafer-level burn-in to ensure the long-term reliability of today's very high-power, high-current AI processors. We're also actively engaged with multiple additional AI processor companies on benchmark evaluations and expect to make meaningful progress with those opportunities. Our benchmark evaluation program with a top tier AI processor supplier continues to make good progress, but it's taken longer than we originally expected. This was due to a technical misunderstanding on the clock configurations, which created some challenges with the initial wafer pack designs. While we wish we had been able to catch this earlier, we're taking device data now on their wafers with the current wafer pack design and redesigning the wafer packs to meet the new requirements. We expect to continue to provide them with additional data on this wafer pack design as well as the improved one over the next several months. We have several other companies ranging from suppliers of data center-focused AI accelerator processors to edge AI processors and CPUs that are providing us with information on their devices and roadmaps and asking about our wafer-level burn-in capabilities and recommendations for burn-in of their next generation devices. There is significant interest in doing wafer-level burn-in for devices that are expected to put in advanced packages such as TSMC's COAS-based packages that include other dyes such as HBM DRAM stacks, other compute AI processors, and photonic or electrical-based transceiver chipsets. Weeding out bad devices before they're packed together with these other devices is significantly cheaper than the yield loss if these are burned in at package level and the entire multi-chip package is thrown away. For burn-in of silicon photonics devices, we recently announced a major new customer win, a major new silicon photonics customer with an initial order for multiple high-power FoxXB wafer-low burn-in systems for devices aimed at the hyperscale data center optical interconnect market. This customer is developing advanced silicon photonics-based transceivers for data center networking and optical I.O. applications to address the rapidly accelerating demand for high-speed fiber optic communication links in hyperscale AI and cloud data centers. These multiple systems are for both engineering qualification and high-volume production and include a Fox XP wafer-low burn-in system configured to test nine wafers in parallel, a fully integrated wafer pack auto-aligner, multiple Fox NP wafer-low burn-in systems, and multiple full sets of Fox wafer pack full wafer contactors for production, engineering, and new product introduction. These systems are all scheduled to ship in this fiscal fourth quarter ending May 29-26. They've also provided a forecast for multiple additional XP production systems over the next year as they ramp capacity to support next-generation hyperscale data center deployments. We believe this win positions AI to participate in what could be a significant multi-year expansion of silicon photonics production driven by the growth of fiber optic interconnects in hyperscale AI data centers. Additionally, we received a follow-on order from our lead silicon photons customer for both a new high-power Fox XP wafer-level system and an upgrade of an existing system to our latest high-power fully automated configuration. We now have fully integrated our systems and aligners with their autonomous guided robots that carry around the 300-millimeter FOOPS so the customer can operate in a fully lights-out, hands-free operation. They, too, have given us a forecast for additional production systems as they ramp into next calendar year. As data center architectures scale to support AI, cloud computing, and high performance networking, fiber optic interconnects offer significant advantages over copper wiring, including higher data rates, lower power consumption, longer reach, improved thermal performance, and reduced electromagnetic interference. These advantages are driving rapid adoption of silicon photonics transceivers across hyperscale and enterprise data centers worldwide and increasing demand for cost-effective production-proven burn-in solutions that can ensure device quality and long-term reliability at volume. AIR is the market leader in wafer-level burn-in for silicon photonics transceivers, with a large installed base at leading global semiconductor and photonics companies. The company's RR Fox XP platform enables high parallelism, high temperature, and high-power wafer-level burn-in, allowing customers to stabilize their devices a critical manufacturing process step in the laser diode emitters for these devices, as well as to identify early life failures before packaging to significantly reduce the cost of test. In gallium nitride and silicon carbide power semiconductors, we've been working with our lead GAN production customer on a significant number of new devices aimed at multiple markets that include automotive, automated bus conversion, data center, and electrical infrastructure. This continues to be a great partnership, and we continue to work on and believe we have solved the key challenges with full wafer burn-in of GaN devices on silicon. Wafer-level burn-in of their GaN devices for both qualification and production burn-in is an extremely valuable capability that is critical to their roadmap and plan, and we're both very excited to see them meet their growth projections. We continue to see GaN and silicon carbide power semiconductors as critical to the electrification of the world's infrastructure in addition to key market opportunities such as data center power delivery, electric vehicles, and charging infrastructure. We want a new customer in silicon carbide this quarter with a company in Taiwan focused on the Asian and particularly greater EV market, greater China EV market, sorry. They placed an order for a small configured Fox XP system For qualification and production, key elements of their decision included our ability to demonstrate all the capabilities they needed with our systems in Fremont, California, as well as the feedback they received from customers who had data and confidence in AIR's wafer-level burning systems used for testing and burning silicon carbide wafers across a large number of silicon carbide suppliers. We see an uptick in activity and forecasts from the silicon carbide players. This makes sense as we see major OEM EV suppliers in Japan and Germany roll out a number of new EVs later this year. These EV suppliers understand the value and need for wafer-level burn-in of these six devices before they're put into modules containing many devices in parallel for the EV engine drive inverters. This is well understood in the industry, and AIR is seen as the market leader and proven solution for wafer-level burn-in silicon carbide devices used in EV inverters by a significant number of EV suppliers. We're still conservative about forecasts from customers. And while we have plenty of capacity and believe we have the world's most cost effective and highest performance wafer level burden solution on the market, we're not yet counting on significant revenue from this segment to return yet. However, it could still be a very good performing segment for us next year. We'll see. Now let me talk about wafer-level burn-in for memory. Our engagement with a key memory supplier continues to progress with additional wafer testing just this last week. We've been able to achieve the correlation they're asking for are now in discussions about test system specifications needed for their next-generation flash memories, and in particular their high-end with flash devices. We hope to close on this in the next few months which would lead to a development agreement to supply systems and wafer packs to them after a 12 to 18 month development of our new memory optimized blades for our Fox XP and NP multi-wafer test and burn-in platform. But we're also now in discussions with other key memory suppliers that also produce high bandwidth memory. The new DRAM standard being used in AI GPUs in addition to standard DRAM and flash memories. The HBM memories, as they're referred to, are embedded into multi-chip packages with advanced substrates, such as the CoAS packaging from TSMC. NVIDIA's roadmap is aggressively pushing toward higher capacity, faster HBM standards to address the memory wall in AI training and inference. The upcoming roadmap transitions from HBM3e to 4 in 2026. and then from HBM4E and HBM5 in the following years, with capacity per GPU expected to increase from 80 gigabytes in the A100 class to over a terabyte in the Rubin Ultra by 2027 for semi-analysis. We are seeing the added potential for HBM insertions with our FOX multi-wafer test and burn-in system roadmap that extends to flash, high bandwidth flash, DRAM, and HBM memories. This is a key focus for AIR this year, to drive to an agreement to work with these customers in the development of the enhancements needed to extend our FOX systems to these markets. This is a market that we believe could drive orders in fiscal 27 with ramps in fiscal 28. Now turning to package level burn-in. Let me start by highlighting that we're trying to change our own vocabulary from package part burn-in to package level burn-in. This may seem subtle, but to give a little background, traditionally there was one semiconductor integrated circuit per single package. The package was used to protect the die from elements and wire out to a standard pattern of pins or pads that allowed easy handling and assembly onto a printed circuit board. This pattern or pitch between pins is much, much larger than the pitch on the individual die. So contacting the devices is very different for us between our package level and wafer level solutions. Historically, about 20 years ago, there was a package concept called multi-chip packages where multiple individual die were wire bonded into a single package. This was driven at the time for size and performance. Typically, this was much more expensive and generally this faded out in time to other smaller package sizes. Recently, in the last handful of years, there have been three major drivers of the need for new multi-chip packages. but this has been called advanced packaging or modules rather than MCPs. One driver, which is the biggest one, is that the multi-decade long trend that was referred to as Moore's Law has come to an end. This law was the number of transistors was doubling every one and a half to two years while the die size was staying the same and therefore costs were staying flat or decreasing. This allowed higher and higher performance, smaller die, and therefore lower cost die to be made via process improvements or die shrinks. This drove the industry for 40 years or so until around 2010 plus or minus when shrinks started to slow materially. Then as several applications such as AI processors, extremely high density memory such as flash and DRAM, power semiconductors were being driven by massive markets such as data center, AI and electric vehicles. The extremely high value and need for multiple devices in the same package came to fruition. This time it was functionality and feasibility that drove this. We now refer to these devices in two camps, really three camps, wafer level, die level, and package level. Where package level includes both single die per package and also multi-chip modules or advanced package multi-die packages such as those found in AI GPUs with HBM DRAM stacks. multi-stack flash SSDs, and also multi-diacyl and carbide modules for EV inverters and charging infrastructure. At least I hope this helps as we talk through this and make it more clear what the difference is between wafer level and package level. You may catch me still saying package part at times as old habits are hard to break, but we'll try to refer these as package level from now on. Okay. During the quarter, we announced a key production win with our lead package level hyperscale customer. This customer is a premier large-scale data center provider and selected air for production burn-in of their next generation significantly higher power AI processor with an initial production order of our high power Sonoma systems. This next generation AI ASIC is expected to move to production later this year and is believed to be even higher volumes than the first device that this customer is ramping our Sonoma systems on right now. We also expect a significant near-term follow-on order from this customer for package-level burn-in systems to support their high-volume manufacturing of their custom AI processors today, the current one used in data center training and inference. They are forecasting a substantial expansion of Sonoma Systems purchases beginning the second half of calendar 2026 and continuing into 2027. We believe it's likely that there is overlapping ramps between the current and next-generation devices, which should significantly expand both our install base and long-term consumable opportunity with this customer. We're also engaged with multiple potential customers for package-level qualification tests of AI accelerators, ASICs, network processors, and edge AI processors for automotive and robotics. These engagements also represent opportunities to move to production burden over time And interestingly, about half of these have also expressed interest in wafer-level burn-in in addition to our package-level burn-in solutions. Yesterday afternoon, in fact, we received an order from a brand new customer for Sonoma to be used for reliability qualification of their new AI processor. But they may also do production burn-in with this device, which they can do with the exact same platform using Sonoma. This momentum reinforces our leadership in high-power burn-in for AI processors. The broader demand environment remains very strong. Industry forecasts indicate that hyperscale data center capacity expected to nearly triple by 2030, driven by both new builds and upgrades to existing infrastructure. This is driving substantial growth in high-performance semiconductors and, in turn, demand for advanced burn-in solutions. As we've noted before, As our install base of systems continues to grow, our consumables, which includes our wafer pack, full wafer contactors for wafer level, and our burn-in board and modules for package level burn-in, can continue to grow beyond our systems. While this year has been lighter in terms of consumable sales, particularly wafer packs, we believe it's an outlier. Some customers had bought systems ahead of the need and have grown into capacity, and this seems to be running its course. We believe over time our consumables business will consistently be at 30% or more of our total revenue, and our margins will increase as sales of these value-add consumables grow. To support growing demand, we're continuing to scale manufacturing capacity. In addition to our Fremont expansion, this quarter we'll begin shipping Sonoma systems from one of our current contract manufacturers, adding capacity of more than 20 additional Sonoma systems per month. This meaningfully increases our ability to support future growth. With expanding AI infrastructure deployments and our recent manufacturing capacity enhancements, we believe we're well positioned to support significant growth both in our wafer level and package level burden systems as customers ramp production. With strong second half booking so far and a strong funnel of additional orders expected this quarter, We believe we're well-positioned to exit the fiscal year ending May 29th with a strong backlog and deliver significant revenue growth in fiscal 27. We currently expect full-year fiscal 26 revenue to be on the high side of the $45 to $50 million range provided last quarter. We also expect our bookings for the second half of the fiscal year to be on the high side of the $60 to $80 million range provided last quarter. More broadly, we believe we have a clear path to sustain long-term growth as our installed base expands across AI, silicon photonics, power semiconductors, memories, and other high-performance applications. As semiconductor performance and reliability requirements continue to rise, burn-in is becoming increasingly critical across a growing set of applications. We believe AIR is uniquely positioned as the only provider offering both wafer-level and package-level burn-in solutions at scale. That'll turn it over to Chris.