Atomera Incorporated

Hello, everyone, and welcome to Atomera's first quarter 2026 update call. I'd like to remind everyone that this call and webinar are being recorded, and a replay will be available on Atomera's IR website for one year. I'm Mike Bishop with the company's investor relations. As in prior quarters, we are using Zoom, and we will follow a similar presentation format with participants in the listen-only mode. We will open with prepared remarks from Scott Vivo, Atomera's president and CEO, and Frank Lorenzio, Atomera's CFO. Then we will open the call to questions. If you are joining by telephone, you may follow a slide presentation to accompany our remarks on the events and presentation section of our investor relations page on our website. Before we begin, I would like to remind everyone that during today's call, we will make forward-looking statements. These forward-looking statements, whether in prepared remarks or during the Q&A session, are subject to inherent risks and uncertainties. These risks and uncertainties are detailed in the risk factors section of our filings with the Securities and Exchange Commission, specifically in the company's annual report on Form 10-K filed with the SEC on February 24, 2026. Except as otherwise required by federal securities laws, Adam Merritt disclaims any obligation to update or make revisions to such forward-looking statements contained herein or elsewhere to reflect changes in expectations with regards to those events, conditions, and circumstances. Also, please note that during this call, we will be discussing non-GAAP financial measures as defined by SEC Regulation G. Reconciliations of these non-GAAP financial measures to the most directly comparable GAAP measures are included in today's press release, which is posted on our website. Now, with that, I'd like to turn the call over to our present CEO, Scott Vivo. Go ahead, Scott.

Thanks, Mike, and good afternoon, everyone. This quarter, we made solid progress with multiple customers across our highest value markets, while also expanding the breadth of applications where MST can solve real current pain points for the semiconductor industry. We're seeing strong customer pull in advanced logic, memory, in wideband gap materials like GAN and power, and in RF, areas that are being shaped by the rapid growth of AI infrastructure, which is driving the need for better power efficiency, signal integrity, and system performance. Today, I'll start with an update on GATE All-Around, where we've been working closely with customers and our strategic partners to validate MST in these advanced geometries. Then I'll touch on our customer pipeline and close with updates on GAN, giving insights on some exciting new technical results that are shaping near-term opportunities. As we've said before, the move to GATE All-Around at 2 nanometers and beyond is one of the most important architectural transitions in the industry, and it's also one of the most difficult manufacturing environments, since fabs must build incredibly complicated structures at line widths of 5,000 times smaller than a human hair, where a small amount of atomic migration can cause big problems. Gate-all-around transistors are the building blocks for AI infrastructure, and dopant diffusion control is critical to their effectiveness in terms of performance and reliability. Therefore, the industry is demanding clear proof that any new material can be deposited precisely and that it delivers measurable benefits in advanced silicon devices. Today, there are four companies in the world developing gate all-around transistors, TSMC, Samsung, Intel, and Rapidus. We know that each of them can use the capabilities of MST So it's our goal to achieve adoption at all four. Further, as these companies transition to the generation beyond gate all around called CFET, our technology becomes even more essential. So working with us now is in our best interest long term. In our last earnings call, we have just received measured silicon results that prove MST is the best solution for a critical source drain liner application in these small geometry transistors. At this point, we're actively working on evaluations of our technology with two of our target gate-all-around customers, and discussions are underway with the others. It is typical that a customer asks to conduct multiple demonstrations before agreeing to accept a new technology for implementation in the FAB's wafer flow. These demonstrations help to validate our claims while simultaneously addressing the detailed implementation and functionality questions these customers are focused on solving. We also expanded the scope of our work with our strategic development partner this quarter, which is important because it strengthens both our technical velocity and our credibility with the ecosystem. Their test and development infrastructure helps us generate the kind of data that advanced node customers insist on seeing before engaging, and their endorsement will certainly help us engage a broader set of teams within each target account. Each of the large memory manufacturers are facing similar challenges to the gate all around customers as they develop their next generation transistors in DRAMs and high bandwidth memories. Our team is in discussions with them right now, and we are currently working on multiple solutions using MSE to assist in this area. Right now, memory manufacturers would do almost anything to get greater fab capacity, and they have the resources to evaluate different methods of doing so. We hope to take advantage of that opportunity with solutions enabled by MSD. The momentum we're seeing in the advanced node transistor space is the result of many years' work targeting current market trends. The macro challenges that AI success has put front and center, capacity and performance of CPUs, GPUs, logic, and memory, the power demands of cloud providers, and the increased costs associated with these, are all areas that Adameric can help solve. For that reason, we believe that MST is a fundamental tool for the future of AI. Our customer pipeline remains very active across multiple domains. For example, our work with our large IDM customer continues to go well, and we expect additional results from wafer runs soon. Our efforts with STMicroelectronics are bearing fruit, and we are confident we will re-engage with them again in the near future, consistent with our view that MST can create value across multiple product lines, especially in a large, diversified IDM or foundry. In RFSOI, we are seeing strong results confirming our extensive TTAD simulations. The technical results we've been focused on, including for both PowerSwitch and LNA, have been confirmed through customer silicon runs. The near-term question is less about performance and more about the most efficient path to commercialization, particularly in cases involving fabulous licensees where aligning the business structure with the manufacturing flow can be complex. In power devices, we are seeing excellent potential in new development work being done to target MST at both trench bed and HVT transistors. useful in high-frequency, high-speed, and high-voltage applications. At the same time, wafers continue moving forward with our second JDA partner, and we'll keep pushing those efforts toward production pathway. Turning to GAN, we made meaningful advancements this quarter, including a breakthrough that could give us a technical leadership in RF GAN on silicon to augment the advances previously outlined for power GAN on silicon To explain the innovation, I need to give a little background. GAN on silicon is a much more economical growth method than alternatives built on exotic substrates like silicon carbide or sapphire. But when GAN on silicon is manufactured, due to the GAN stack growth process, gallium and aluminum ions gather at the silicon substrate interface, forming an unwanted sheet charge layer called a parasitic channel which is well known to limit RF performance in GaN on silicon applications. In fact, its elimination has been the subject of materials and growth studies for more than 20 years. In the past few weeks, we received preliminary performance data suggesting MST can dramatically reduce the parasitic channel. It does this by using MST's fundamental interface engineering to block the gallium and aluminum ions from getting into the silicon substrate. An industry veteran told us that in his 20 years, this is the best measured sheet charge data he has ever seen. We're continuing to validate this very promising discovery with our test and measurement partners. RF GAN on silicon is of value in the wireless infrastructure, military, defense, and satellite markets. It's also being actively evaluated for high integrated RF front ends such as those for 6G cellular. So the market potential is large and growing fast. We are actively engaging on both 200 millimeter and 300 millimeter wafer sizes in GaN depending on our customers' requests. That matters because the wafer size for GaN on silicon is one of its key advantages leading directly to a customer's path to high volume production, low cost structure, and a set of fabs that can support RAMP, including opening doors for new applications with conventional silicon fabrication methods and devices. We're seeing expanded interest in partnerships across the ecosystem, including engagements involving InSize, Synopsys, Texas State University, Sandia, and others. Those kinds of parallel paths, commercial customers plus research and ecosystem partners, can compress development cycles and accelerate the time from promising materials data to something customers can qualify and deploy. Work here is aimed at generating data that is both technically rigorous and directly translatable to customer device requirements. Finally, a quick note on our announcement last week about expanding our collaboration with Synopsys. We've worked with Synopsys for years to enable accurate modeling of MST inside the Centaurus keycat environment, through our MSD CAD tool set. This expanded collaboration extends that relationship into GAN workflows for both high-value RF and power devices. Practically, this means we're working closely with Synopsys to provide feedback on their GAN models, and we'll be jointly developing marketing materials so customers and partners can evaluate the physical and electrical effects of MSD and GAN more quickly and with higher confidence. To summarize, we're making progress where it matters, expanding and deepening gate-all-around engagements, broadening GAN from power into RF with concrete technical innovations, and continuing to advance multiple customer programs across our pipeline. We remain focused on converting technical validation into commercial structures that can drive repeatable revenue and are confident in our ability to do so. This is indeed an exciting time for AtomEra. With that, I'll turn the call over to Frank, our CFO, to review our financials.

Thank you, Scott. At the close of the market today, we issued a press release announcing our results for the first quarter of 2026, and this slide shows our summary financials. Our gap net loss for the first quarter of 2026 was $6.1 million, or 17 cents per share. compared to a net loss of $5.2 million, which was also 17 cents a share in Q1 of 2025. On a non-GAAP basis, net loss last quarter was $4.9 million, or 14 cents a share. And our Q1 2025 net loss was $4.4 million, or 15 cents a share. GAAP operating expenses were $6.2 million in Q1 of 2026, which was an increase of $742,000 from $5.5 million of GAAP operating expense in Q1 2025. Stock compensation expense, which is excluded from non-GAAP results, increased by $397,000, primarily due to new hires and our adoption in Q1 of 2025 of performance stock units, or PSUs, for executives. PSUs vest over three years, whereas the time-based options and RSUs that we had previously granted to executives vested over four years. Although the vesting period is shorter, PSUs vest only if our stock performs well relative to the Russell 2000. The first tranche of PSUs issued in Q1 2025 lapsed without vesting because we did not hit the required stock price performance threshold. With the exception of stock compensation expense, the drivers of GAAP and non-GAAP expenses are substantially the same. So I will drill down into other factors that impacted our expenses by focusing on non-GAAP numbers. Please refer to the slide presentation for reconciliation between GAAP and non-GAAP results. Non-GAAP operating expenses in the first quarter were $4.8 million. a year-over-year increase of $348,000 from $4.4 million in Q1 of 2025. Sales and marketing expense increased by $203,000, reflecting our two executive hires since October. R&D expenses increased by $127,000 from $2.8 million in Q1 of last year to $2.9 million in the first quarter of this year, primarily due to higher spending on outsourced engineering, to support the wafer runs for our gate-all-around engagements, our IDM customer, and our JDA customer, which drives spending on metrology. G&A expenses were basically flat from the first quarter of last year. Turning to sequential quarterly results, first quarter 2026 non-GAAP net loss was $4.9 million, or 14 cents a share, compared to net loss of $3.3 million, or $0.10 a share in Q4 of 2025. Operating expenses were $4.8 million in Q1, which is a $1.6 million increase from $3.2 million in Q4. Let me offer some color on the magnitude of this sequential increase. As I explained on our last quarterly call, our compensation committee elected not to pay the full 2025 executive bonus. withholding approximately $669,000, which normally would have been paid out in January. The committee provided the executive team the opportunity to earn back the withheld amount in 2026 upon achievement of commercial objectives. This led to us reversing accrued bonus expense in the fourth quarter, which skews the comparison of expenses between Q1 and Q4. Our balance of cash, cash equivalents, and short-term investments on March 31, 2026 was $41.1 million, compared to $19.2 million on December 31, 2025. We used $4.6 million of cash in operating activities during Q1, compared to $3.2 million in Q4, and $4.8 million in Q1 of last year. As is typical for us, cash use in the first quarter of every year is higher than other quarters due to payments for items that are expensed over the year. In February of this year, we closed on a $25 million registered direct stock offering, selling 5 million shares of common stock at $5 per share, netting us proceeds of $23.6 million after fees and expenses. Prior to this offering, we had also raised $3.2 million in Q1 by selling approximately 1.3 million shares under our ATM at an average price of $2.47. Currently, we have 38.7 million shares outstanding. With the proceeds of our equity offering, we feel that our current cash balance puts us in a strong position to execute on the opportunities ahead of us. but we will continue to be disciplined about controlling our costs. On our last call, I said that we expected our 2026 annual non-GAAP operating expense to be approximately $18.5 million, and we are holding to that number. To reiterate, the reason why the expense increase appears as large as it does over $15.9 million of OPEX in 2025 is is the bonus deferral, which essentially shifted expenses out of Q4 and moved them into 2026. Organic increases in spending mainly relate to the hiring of our VP of sales in Q4 last year and our VP of marketing in Q1. Revenue in Q1 was $11,000 and consisted of fees for wafer deliveries to the large IDM that Scott talked about. and we have $96,000 of deferred revenue on our balance sheet. Approximately $46,000 of revenue that we expected to recognize in Q1 pushed out to Q2 because wafer shipments that we anticipated making last quarter pushed out to early this quarter. Accordingly, we expect Q2 revenue to be in the range of $50,000 to $100,000. With that, I'll turn the call back over to Scott for a few summary remarks before we open the call up to questions.