QuickLogic Corporation

Ladies and gentlemen, good afternoon, and at this time, I would like to welcome everyone to QuickLogic Corporation's third quarter fiscal 2024 earnings results conference call. As a reminder, today's call is being recorded for replay purposes through November 18, 2024. I would now like to turn the conference over to Ms. Allison Zeigler of Darrow Associates. Ms. Zeigler, please go ahead.

Thank you, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited to stated expectations relating to revenue from new and mature products, including the expected timing of such revenue, statements regarding our future profitability and cash flows, statements regarding the timing, milestones, and payments related to QuickLogic's government contracts, statements pertaining to QuickLogic's future performance, design activity, and its ability to convert new design opportunities into production shipment, timing and market acceptance of its customers' products, schedule changes and production start dates that could impact the timing of shipment, the company's future evaluation systems, broadening the number of our ecosystem partners, and expected results and financial expectations for revenue, gross margin, operating expenses, profitability, and cash. Actual results or trends may differ materially from those discussed today. For more detailed discussions of the risks, uncertainties, and assumptions that could result in these differences, please refer to the risk factors discussed in QuickLogic's most recent refiled periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR webpage that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR webpage shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our third quarter 2024 conference call. We have made tremendous progress during the first 10 months of 2024, and we have a number of significant contracts in process that we believe we will win in the coming months. The most significant of these contracts that we expected to be awarded earlier this quarter has been delayed to later this quarter. The primary reason for this delay is its expanded scope. While this expansion is clearly good news, the delay will push the majority of the revenue recognition into Q1 2025. As a result, our revenue guidance for Q4 will be $6 million. Following my review of major contracts and other updates, Elias will cover our Q4 revenue guidance and other financial measures which will include our forecasted return to non-GAAP profitability in Q4 and for full fiscal year 2024. Last Friday, EE Times published an article announcing that analog devices will acquire the assets and technical team from our primary eFPGA-IP competitor, FlexLogix. According to the article, FlexLogix eFPGA-IP has been used by ADI for a long time and there is an intent to extend the use of eFPGA across ADI product lines. Based on the information in this article and other inputs, we believe ADI will discontinue external licensing of FlexLogix IP. With eFPGA customers likely having advanced notice of this news, we have seen an influx of inquiries from large companies for applications targeting fabrication processes for which we've already developed eFPGA hard IP. Given these circumstances, we believe contract negotiations will be fast tracked and with eFPGA hard IP already established, we can deliver customer specific IP quickly. Also very notable is the fact FlexLogix was the only other eFPGA company that was announced as a member of both the Intel Foundry's Accelerator IP and U.S. Military, Aerospace, and Government, or USMAG, alliances. This bolsters our confidence that our early investments to develop EFPGA hard IP for Intel 18A will pay off in a big way. On June 18th, we announced that we joined the Intel Foundry's Accelerator IP and USMAG alliances. Driven by customer demand, and to capitalize on the already considerable interest from companies targeting Intel 18A for new designs, we initiated development of our EFPGA hard IP in Q2. We believe this will position QuickLogic to be the first available source for EFPGA hard IP optimized for Intel 18A. We already have two outstanding proposals for Intel 18A designs in the defense industrial base sector, one of which is very significant. We are also in discussions with a very large company in the compute IT sector that we believe will lead to a formal proposal in the near term. Due to our early investments to develop EFPGA hard IP and unique ability to quickly convert that to customer specific hard IP cores, we believe we are well positioned to win Intel 18A contracts and accelerate the schedule of our deliverables. On July 8th, we announced the award of the third tranche of the strategic radiation hardened FPGA government contract. We anticipate the fourth tranche will be awarded this quarter and expand the scope of the long-term contract that was initiated in 2022. The total potential for this contract, including future options, is $72 million. If these options are exercised, we expect the funding rate will increase beginning in 2025. During the first quarter of 2024, we announced two contracts that will be fabricated using a 12 nanometer process. The first contract is with a defense industrial based customer and includes two cores that will be fabricated on Global Foundry's 12LP process. As we forecasted last quarter, we completed our initial deliverables for the first core during Q3 and are on schedule to complete our work on the second core during Q4. We anticipate further revenue recognition in Q2 2025 as the customer does test chip preparation. The second contract is with a large, well-known international company. This design is for a new ultra-low power SOC that is targeting a variety of commercial and industrial IoT AI applications. This design will be fabricated by TSMC on its 12-netometer process. We completed our deliverables on this contract and recognized the associated revenue during Q3. We believe we'll have more clarity about the potential of a second design once the test chip for the first design is completed during Q1 2025. In November 2022, I shared that we taped out a new device for a customer that incorporates our eFPGA hard IP. This contract was announced in June 2022 with the stated expectation that revenue would extend to June 2025 with follow-on storefront revenue expected after the completion of the IP contract. In line with what I covered during our last conference call, due to a delay with one of the customer subcontractors, we believe we will resume work on this design during the second half of 2025. This program is still a solid go and could represent tens of millions of dollars in store for revenue starting in a couple of years. In September 2023, we announced the leading technology company chose our eFPGA hard IP for design that will be fabricated using Global Foundry's 22FDX platform. The customer has completed its design, expects to take out later this quarter, and receive test chips from Global Foundry during the first half of 2025. If all goes as planned, that will lead to our revenue recognition of a production license during the second half of 2025. In November 2023, we announced a global semiconductor leader chose our eFPGA hard IP for design that will be fabricated on UMC's 22 nanometer process. We delivered our IP earlier this year and test chip evaluations are going very well. We anticipate being involved in their marketing efforts during Q4 2024 and Q1 2025. We expect these efforts will generate IP revenues for QuickLogic in 2025 and royalty revenue beyond in addition to these awarded contracts we have a number of large contract proposals pending some valued in the mid seven figures these include proposals in a variety of critical infrastructure sectors and a proposal with a large semiconductor company some of these proposals are potential storefront designs in total we have delivered our australis generated EFPGA HART IP on five unique process technologies funded by customer contracts. These include Global Foundries 12LP, TSMC 12nm, Global Foundries 22FDX, UMC 22nm, and Skywater RH90. Additionally, we believe we are on track to be the first company to offer EFPGA HART IP for Intel 18A. Given the fact these include some very popular high volume process technologies, this is a big deal. Once we establish our eFPGA hard IP for a given process technology, our proprietary Astralis eFPGA hard IP generator can deliver customer-specific eFPGA hard IP rapidly, in some instances within days. This positioning provides multiple advantages. First, it enables us to further leverage the investments we've made to establish eFPGA hard IP for a given process technology. second it enables us to respond quickly to opportunities and that lowers our costs associated with proposals third it increases our market reach as potential customers know we have a proven solution that can be deployed in a very short period of time we expect these benefits will accelerate our growth profitability and market penetration to that point i'm often asked what about the market sectors we are serving As it stands today, we have active production IP contracts in the defense industrial base, or DIB, communications and industrial sectors, and a test chip IP contract in the mass transportation sector. In addition to these, we have outstanding production IP proposals in the DIB, communications, industrial, compute, IT, and mass transportation sectors. These market sectors, which fall under the critical infrastructure umbrella, share common traits. They all have long design cycles, very long production life cycles, are pervasive users of programmable logic and ASICs, and are more focused on capabilities than cost. You will see examples of critical infrastructure applications we are targeting on our updated website that will go live later this month. The US Department of Defense and Department of Commerce fund a variety of contracts to advance technology. The primary focus for the DOD is to fund product developments that will be used by its DIB contractors. The Department of Commerce has a broader agenda. We have three outstanding proposals for advanced technology initiatives that fit well in our core business strategy. In addition to our proposal for the fourth tranche of the strategic router contract that we want as the prime contractor in 2022, we also have two proposals pending where we partnered with very large companies that submitted the bids as the prime contractor. These proposals, while exciting, are too early in the process to expand upon. In past conference calls, I referenced two Chiplet proposals as having a combined potential value of $40 million. We recently learned that we were not selected. As best we can tell, these proposals did not elect to incorporate FPGA technology. The value of these proposals has been removed from our funnel and only partially replaced with new opportunities. As a result, our funnel value as of today is $164 million. The shiny side of this coin is that several of the new opportunities are inbound inquiries from very large companies for fully funded programs that have committed to using eFPGA and are targeting fabrication processes for which we already have eFPGA hard IP. Due to these factors, I believe our odds of winning are very high, and in at least one case, the contract could move forward quickly. We remain very optimistic about the future of merchant chiplet designs. Chiplets are already being used by large semiconductor companies like AMD, Intel, and Nvidia in high volume, but for the most part, these are vertically integrated designs. In my recent communication with Kash Johal, CEO of YourChip, he stated that merchant chiplet designs will build traction in 2026, and he believes that together, We are well positioned to be a leader in low power edge designs that require programmability. We anticipate the first jointly developed eFPGA chiplet integrating QuickLogic IP in second half of 2025. Going forward, this eFPGA chiplet product line will be expanded to include devices ranging from 40,000 LUTs to over 1 million LUTs. All of these designs will use the industry standard high speed UCIE chiplet interface, which is supported by most of the largest tech companies in the world. In line with our earlier forecasts, shipments of EOS S3 to our lead smartphone customer increased during the first half of 2024, and as we forecasted, Q3 should be a low point for the year. We anticipate shipments will sequentially increase in Q4 and again in Q1 2025. In a recent meeting at our headquarters, our customer identified new designs that could extend revenue into 2026. Consistent with our prior outlook, we are forecasting a modest increase in display bridge and mature product shipments for the full year 2024. In our last conference call, I discussed three new distribution agreements intended to expand our coverage internationally and enhance our coverage of the U.S. DIB. In October, we added Magenta to broaden our coverage in Turkey and UAE. Magenta specializes in customer-specific solutions for military and aerospace companies. The unique market focus and capabilities of these distributors is already yielding results. In the short time since they joined the QuickLogic team, they have collectively initiated several well-qualified eFPGA IP design opportunities with a combined value of approximately $2.5 million. They are also working with customers on new discrete FPGA and EOS S3 opportunities. Aurora is our comprehensive software tool suite comprised of open source and proprietary components that is used by our customers for eFPGA design. It provides seamless integration from customer RTL to eFPGA or FPGA bitstream. In line with our previous forecast, we released version 2.8 during Q3 and are on schedule to release version 2.9 during Q4. Driven by current strategic customer demand, We have entered into a contract with Synopsys to license its Simplify FPGA synthesis software. We will integrate Simplify in our Aurora tool suite for lead customer beta testing this quarter with full release expected in Q1 2025. Synopsys will enhance its Simplify tools to support our unique QuickLogic eFPGA architecture, which will enable customers that use Simplify to work in a familiar design flow environment. Simplify will also enable customers to further optimize QuickLogic EFPGA designs for power, performance, and area, broadly known as PPA. In some applications, these are critical factors, so integrating Simplify will expand our available markets. Turning now to Sensible. As we covered in our last conference call, Sensible has launched Piccolo AI, the first complete open source AutoML solution for the development of Edge AI ML applications. Sensible also launched its generative AI feature that enables developers to rapidly build ML training data sets for custom voice recognition, voice command, and speaker identification applications. Through a close collaboration with Sensible, eFabulous announced last month the launch of ChipIgnite ML, a new system on chip platform that is optimized for Sensible software. The prototype run of this new SOC solution is scheduled for April 2025 with production to follow. On October 10th, Sensible announced its support for RISC-V. With RISC-V support, developers can now use Sensible's open source Piccolo AI AutoML tool to create ultra-efficient machine learning models tailored to specific applications using open source RISC-V hardware. Sentinel is collaborating with two top-tier microcontroller companies to enable its AI and all development tools on their edge platforms and planned AI accelerator SOCs. With that, let me now turn the call over to Elias for a review of the financial results, and I will rejoin for our closing remarks. Elias, please go ahead.