QuickLogic Corporation

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everyone to the QuickLogic Corporation's third quarter fiscal 2025 earnings results conference call. As a reminder, today's call is being recorded for replay purposes through November 18th, 2025. I would now like to turn the conference over to Ms. Allison Ziegler of Darrow Associates. Ms. Ziegler, please go ahead.

Thank you, Vaughn, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited statements regarding our future profitability and cash flows, expectations regarding our future business, and statements regarding the timing, milestones, and payments related to our government contracts, statements regarding the use of the company's ATM program, and statements regarding our ability to successfully exit Sentinel. Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time to market of our new products, intense competition from competitors, our ability to hire and retain qualified personnel, changes in demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could cause disrupt supply or delivery of or demand of the company's products, and changes in tax rates and exposure to additional tax liabilities. For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please revert to the risk factors discussed in QlikLogic's most recently filed periodic reports with the SEC. QlikLogic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We've also posted an updated financial table on our IR webpage that provides current historical non-GAAP data. Please note, QuickLogic uses its website, public blogs, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR webpage shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our third quarter 2025 conference call. We have made very significant progress since our August conference call. Last quarter, I stated that we focused considerable engineering resources to accelerate storefront design wins for our strategic Rathart FPGA and expand our served available market to include very high density EFPGA hard IP designs targeting advanced fabrication nodes. I am proud to say our engineering team has executed beautifully, and we are realizing these goals. We expect to begin recognizing storefront revenue in early 2026, and that it will provide a meaningful contribution to total 2026 revenue. The interest from large defense industrial-based entities, or DIBs, in the SRH test chip we funded is notably higher than I anticipated. We have significantly expanded our ability to address the lucrative markets for very high-density discrete FPGAs and ASICs that require large blocks of eFPGA. New contracts and engagements are for much larger blocks of eFPGA and on advanced fabrication processes. The value contribution of eFPGA in customer designs has grown substantially. Our penetration in commercial market sectors is expanding, and with this progress, the rate of new contract closure is accelerating to the point that license revenue may surpass NRE revenue for the first time this quarter. We believe these trends will accelerate going forward. Before I get into the tangible data that support these points, I want to take a moment and provide some color for the revenue guidance Elias will share in his presentation. Based on our backlog and forecasts provided to us by our customers, we are targeting total revenue of $6 million for Q4. The majority of the contracts that support this outlook are already on the books or have been forecasted by customers to be awarded during the coming weeks. However, a contract valued at nearly $3 million for a commercial application targeting an advanced fabrication node has been forecasted by the customer to be awarded late in the quarter. If this contract is awarded on or very near the date forecasted, we will be able to recognize a large portion of that revenue in Q4, and with that, realize our $6 million objective. We have a very high level of confidence in winning this contract. But note that it could push into Q1 2026, and that would result in lower Q4 2025 total revenue. Due to this, Elias will present an unusually wide guidance range. And now let's walk through our accomplishments. In early August, we delivered design files to GlobalFoundries to fabricate our SRH FPGA test chip using its 12LP process. This test chip was designed to meet the requirements of certain large dibs that have programs in development today that are good candidates for this device. We expect delivery of test chips in early Q1 2026 and believe we will have our SRH dev kit ready for shipment to customers shortly thereafter. This initiative was financed by QuickLogic and is independent from our contract with the U.S. government. Our decision to invest the money and resources to develop this test chip was based on our belief that it is critical in our quest to secure strategic design wins and accelerate our storefront business model. Since our last earnings conference call, I have personally met with a number of the DIBs that worked with us through the development process, and I cannot emphasize enough the potential of our SRH storefront initiative. In prior meetings, all I had to show were PowerPoint presentations. And now with a test chip in fabrication, the level of enthusiasm is palpably higher. As a matter of fact, we already have commitments for SRH dev kit orders that we expect to receive by the end of this month. I see this as our first tangible step towards the hundreds of millions of dollars in potential storefront business we could win in the coming years. The importance of demonstrating our SRH FPGA test chip goes well beyond the storefront designs we believe it will enable us to secure. FPGA is the number one spend category for semiconductor devices by the Defense Industrial Base, and custom ASICs are a close second. Together, we believe these two categories make up roughly half of the DIB semiconductor TAM. We expect many of the new strategic designs that require various levels of radiation hardness We'll use either discrete FPGA devices that we can store front or eFPGA hard IP we can license in new ASIC designs. By delivering a discrete SRH FPGA test chip fabricated on the 12OP process, we are demonstrating the broader capability of our eFPGA hard IP for ASIC applications that will meet program requirements ranging from radiation tolerant to strategic rad hard. There are three very important points I want to highlight here. First, DIBs are already using Global Foundry's 12OP fabrication process for radiation tolerant and SRH ASICs. Second, government contracts require the use of onshore fabrication for strategic programs when devices are available. As it stands today, we will be the only source for strategic routered FPGAs and SRH eFPGA hard IP that is fabricated in the U.S. by a U.S. company. Third, in my meetings at large dibs, engineering managers have clearly stated that being able to design with our Aurora FPGA user tools for both our SRH discrete FPGAs and our eFPGA hard IP in ASIC designs is a huge plus. During our last conference call, I stated that Q3 would mark the low point for revenue recognition for our US government SRH FPGA contract this year. Funded by the current tranche, revenue recognition from the contract will rebound significantly in Q4. Beyond that, we anticipate an increase in quarterly revenue recognition in 2026 that will be funded by the next tranche. During our last conference call, I forecasted the award of a mid seven-figure contract from Adib during Q4 that targets Intel 18A. Unfortunately, there has been a delay in funding that pushes this contract into 2026. We are highly confident that we'll be awarded this contract, but at this juncture, our customer has limited visibility on the timing of funding. While we await funding for this seven-figure deal, It is worth noting that we have already been awarded multiple contracts by this strategic customer during 2025. We delivered customer-specific eFPGA hard IP for this customer's first Intel 18A test chip last April. We expect to receive our allocation of test chips from this contract during Q1 2026 for our internal verification and characterization. We were subsequently awarded a mid-six figure contract for a second Intel 18A test chip. We delivered customer-specific eFPGA hard IP for this test chip during Q3. In addition to these Intel 18A test chip contracts, during our last conference call, I announced this customer awarded us a contract for a 1 million LUT feasibility study that we are scheduled to deliver next week. We are anticipating a follow-on order in the coming weeks associated with this feasibility study that will enable the customer to tape out a very high-density Intel 18A proof-of-concept device during the second half of 2026. The architectural changes we implemented in this feasibility study can be leveraged across all advanced fabrication nodes, which we define as 12 nanometers and below. With these changes, we can now address the lucrative markets that require very high-density eFPGA blocks in ASIC design and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA hard IP and discrete devices, including our SRH FPGA, chiplets, and other storefront opportunities. We initiated our digital proof of concept chiplet program earlier this year as a strategy to accelerate our storefront chiplet initiative. Internally, we refer to this as POC. With the support of our large strategic partners, we have leveraged our existing EFPGA hard IP and readily available third party IP to move forward rapidly and with minimal investment. In line with the forecast I shared in our last conference call, we completed the initial phase of the digital FPGA chiplet POC where the eFPGA IP is connected to UCIE IP and the necessary interface logic for the IPs to communicate. This digital simulation of the POC is available now and can be further developed to meet different customer requirements. Together with our ecosystem partners, we are engaging with prospective customers in the defense, aerospace, industrial, and commercial markets. We plan to move forward with the next phases of the FPGA chiplet POC once external funding is committed. This phase will include incorporating additional IP, such as programmable GPIOs, AXI bus, DSPs, data converters, and interfaces such as PCI Express, to meet specific customer requirements. We are optimistic that our POC initiative will lead to storefront revenue in 2026. On October 2nd, we announced a new $1 million EFPGA hard IP contract for a high performance data center ASIC that will be fabricated on TSMC's 12 nanometer process. In this ASIC, our eFPGA hard IP will be the primary IP in the design. This contract is a great illustration of our success in several of the points I mentioned earlier. The need for larger blocks of eFPGA, the increasing value contribution of eFPGA in customer designs, winning contracts for designs targeting advanced fabrication processes, and our growing success in commercial market sectors. We will soon announce the expansion of our involvement with a DIB that specializes in cybersecurity for strategic and tactical weapon systems. This DIB designs secure system-on-chip processors that leverage the enhanced security that only eFPGA can provide. Running these processes and hardware is inherently more secure than software solutions. With eFPGA at the heart of the designs, the hardware can be altered to respond to new threats and updated algorithms. We are proud to have been chosen as a trusted supplier of EFPGA Hard IP for these designs. Last April, we announced an EFPGA Hard IP contract with a new defense industrial base customer valued at $1.1 million that will be fabricated on the GF12LP process. This application utilizes a large block of our eFPGA hard IP for critical functions, which is a trend we are seeing, particularly in designs targeting advanced fabrication nodes. With the cooperation of this Dib and its end customer, we are leveraging the large eFPGA core into a new seven-figure contract we expect to announce in the coming weeks. In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit will be compatible with common third-party development environments used by both TIBS and commercial customers. This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the 12LP test chip or our eFPGA hard IP in an ASIC. We anticipate having evaluation kits available in late 2026. With that, I will turn the call over to Elias for his presentation of financial data.

Thank you, Brian, and good afternoon, everyone. Total third quarter revenue was $2 million and aligned with the midpoint of our guidance. Total revenue was down 52.5% from Q3 2024 and down 45% compared to Q2 2025. Rounded to the nearest 100,000, New product revenue in Q3 was $1 million and mature product revenue was $1.1 million. New product revenue was down 73.1% from Q3 2024 and down 67.3% compared to Q2 2025. Mature product revenue was up from $0.7 million in the third quarter of 2024 and up from 0.8 million in the second quarter of 2025. Non-GAAP gross margin in Q3 was a negative 11.9%. This compared with non-GAAP gross margin of 65.3% in Q3 2024 and 31% in Q2 2025. The primary reasons for the lower Q3 gross profit margin unfavorable absorption of fixed costs due to lower revenue and the fact that $300,000 of R&D costs were allocated to COGS. Non-GAAP operating expenses in Q3 were approximately $2.9 million. This was approximately $300,000 below the midpoint of our outlook due to the COGS allocation I just mentioned. This compares with non-GAAP operating expenses of 3.3 million in the third quarter of 2024 and 2.5 million in the second quarter of 2025. Non-GAAP net loss was 3.2 million or 19 cents per diluted share. This compares to non-GAAP net loss of 0.9 million or 6 cents per diluted share in Q3 2024. and a non-GAAP net loss of 1.5 million or nine cents per diluted share in the second quarter of fiscal 2025. The difference between our GAAP and non-GAAP results is related to non-cash stock-based compensation expenses, impairment charges, and restructuring costs. Stock-based compensation for Q3 was 0.8 million. Stock-based compensation was $1.2 million in Q3 2024, and $0.8 million in Q2 2025. Impairment charges were $0.3 million in Q2 2025. For the third quarter, three customers accounted for 10% or more of total revenue. At the close of Q3, total cash was $17.3 million, inclusive of utilization of $15 million from our $20 million credit facility. This compares with $19.2 million inclusive of usage of $15 million from our $20 million credit facility at the close of Q2 2025. Net of approximately $200,000 raised with our ATM in July, cash usage during Q3 was approximately $1.9 million. This was primarily driven by tip-outs and wafer costs associated with our internally financed SRH FPGA test chip. In addition to these one-time costs, there were also expenditures related to revenue contracts and repayments for finance tooling and equipment. Now moving to our guidance and outlook for our fiscal fourth quarter, which will end on December 28, 2025. Based on backlog and customer forecast, we're targeting total revenue of $6 million for Q4. Many of the contracts that support this outlook are already on the books or have been forecasted by customers to be awarded during the coming weeks. However, the customer for a contract valued at nearly $3 million for commercial application has forecasted the award late in the quarter. If this contract is awarded, on or very near the date forecasted, we will be able to recognize a large portion of that revenue in Q4. And with that, realize our $6 million objective. We have a very high level of confidence in winning this contract, but note that it could push into Q1, 2026, and that would result in Q4 revenue of 3.5 million. Due to this, our guidance range for total Q4 revenue is $3.5 million to $6 million. At $3.5 million, we expect total revenue to be comprised of $2.5 million in new product revenue and $1 million in mature product revenue. At $6 million, we expect $5 million in new product revenue. Based on the anticipated Q4 revenue mix, non-GAAP gross margin for the fourth quarter is expected to be approximately 45% at $3.5 million of revenue and 68% at $6 million of revenue. At the low end of the range, the primary reason for lower gross profit margin is attributed to less favorable absorption of fixed costs. Taking the range of our Q4 outlook into consideration, our full year 2025 non-GAAP gross profit margin is expected to be 38% plus or minus 5%. Our Q4 non-GAAP operating expenses are expected to be approximately 3 million plus or minus 5%. With this, we are modeling full year 2025 non-GAAP OPEX will be approximately 11.3 million. Please note that given the nature of our industry, we may occasionally need to classify certain expenses to COGS. versus OPEX or capitalized certain costs. These classifications are related to labor and tooling for IP contracts with customers. This may cause variability in our quarterly gross margins and operating results that will usually balance out on the operating line. After interest and other income, at the low end of the revenue range, we forecast a Q4 non-GAAP net loss of approximately $1.9 million or 11 cents per share. At the high end of our revenue range, we're projecting a non-GAAP net profits of approximately 600,000 or 4 cents per share. The main difference between our GAAP and non-GAAP results is related to non-cash stock-based compensation expenses. In Q4, we expect this compensation will be approximately 800,000. This is the same as Q3, 2025, and down slightly from Q4, 2024. As a reminder, there'll be movement in our stock-based compensation during the year, and it may vary each quarter based on the timing of grants. Even at the low end of our revenue guidance range, we anticipate positive cashflow in Q4. However, the timing of payments from our US government contract could negatively impact this outlook. Given the fact that we raised approximately $2 million using our existing ATM in October, we're well prepared for any delayed payments associated with the U.S. government contract. Thank you. With that, let me now turn the call over to Brian for his closing remarks.

Thank you, Elias. We have logged considerable progress during the last few months, and we are leveraging that progress to produce tangible results. Earlier, I talked about those results, and now I would like to take the next few minutes to help you understand the industry trends that are driving these results. With that understanding, I think you will appreciate what is driving the increased interest in FPGA technology and why more companies are incorporating larger blocks of eFPGA at the core of new ASIC designs. The overarching trend in both commercial and DIB designs is smart systems. Smart systems rely on algorithms for their intelligence. Algorithms can be processed much faster and with much lower power consumption in hardware than software. Hardware processing is also inherently more secure against cyber threats than software. The challenge here is that algorithms must be updated over the lifecycle of the product. This means hardware must be programmable so it can adapt to changing algorithms. This has led to the need for larger blocks of EFPGA at the heart of ASIC designs versus past use cases where small blocks of EFPGA were more commonly used as programmable connectivity bridges. This means both the need and the value proposition for EFPGA are increasing. Sophisticated smart systems designs typically target advanced fabrication nodes. This means higher fixed costs and longer design cycles for ASICs. To favorably offset these higher fixed costs, ASIC designs must deliver longer life cycles than in the past. Designs that employ eFPGA can adapt to changing algorithms, evolving functional requirements, and external changes that are not evident during the design cycle. This flexibility lengthens the life cycle of ASIC designs and provides program managers with the confidence to move ASICs to production more quickly and with lower risk. This shortens design cycles and lowers development costs. Last but certainly not least, there are many programs in development today that must be compliant with rigorous environmental requirements, ranging from radiation-tolerant to strategic red heart. Our internally funded development of an SRH FPGA test chip is designed to address the full range of these requirements and accelerates our ability to pursue design wins. By using the same onshore 12OP fabrication process that DIBS have used for SRH ASICs, we are optimizing our chances of winning discrete FPGA designs we can store front and contracts for eFPGA hard IP that customers can incorporate in ASIC designs. Further enhancing our position is the fact customers can execute designs with our Aurora user tools for both. The fact this investment by quick logic has been received very well by strategic dibs is underscored by the commitment we have for SRH dev kit orders that we anticipate receiving by the end of this month. Before I turn the call over for Q&A, I want to take a moment to recognize Veterans Day and express my heartfelt gratitude to all those who have served our country. This day has personal meaning for me as several members of my family have served and I have deep respect for the sacrifices made by veterans and their families. It's something we honor at QuickLogic, especially as we develop technologies that contribute to our nation's defense and security. Operator, I would now like to open the call for questions.

Thank you. We will now be conducting a question and answer session where selected analysts will be invited for questions. If you would like to ask a question, please press star 1 on your telephone keypad. a confirmation tone will indicate your line is in the question queue. You may press star 2 if you would like to remove your question from the queue. For participants using speaker equipment, it may be necessary to pick up your handset before pressing the star keys. Our first question comes from Quinn Bolton with Needham. You may proceed with your question.

Hey, everyone. It's Neil Young on for Quinn Bolton. Thank you for letting me ask a question. So the first question I wanted to ask Hey, like I said, I'm for Quinn. Sorry about that. So what impact is the government shutdown having on your business? Based on the prepared remarks, it sounds like you've seen some delays of projects. Have you seen any cancellations? And then, you know, given the ongoing shutdown, although it is allegedly supposed to end soon here, What gives you confidence in a rebound of the USG strategic radiation ARDN FPGA program in 4Q? And then I have a follow up. Thanks.

Yeah, I think firstly, let's zoom out. Programmable logic has been a big part of the defense industrial base for decades, and that's not changing. It's pervasive across like 75% of defense systems. And as I mentioned earlier, a very large percentage of the total semiconductor spend by the DoD. So that demand is not going away. The question is, as you get down to the nuts and bolts of these programs, is the funding going to be there based on the budgets and whatnot? So I think that from the programs that we have today on contract, we're not seeing any delays with those. Elias did mention in his conversation about the cash usage for the quarter, or I should say net cash gain in the quarter, we did use the ATM in October. sort of as an anticipation in case there was something like this that happened as far as funding goes. So if there's a delay in funding, then we have no issue with that. If there's no delay, then we'll have a good positive cash flow for the quarter. Aside from that, if you look at other contracts coming down the pipe, I mean, you could find this all publicly that a lot of the new RFIs or RFSs or RFPs that were coming out from the government for various development programs, Some of those were actually paused, and I think that's largely because some of those workers that were driving that were put on furlough. Again, I don't anticipate those going away permanently. It's more once the government's funded and people get back from furlough, these are going to be full steam ahead. So you might see a delay in some of those new programs, but not the ones that we're fully executing on today. I just don't see that change because this is not an experimental technology. There are actual programs of record that need this today and moving forward on that. Does that answer your first question?

Yeah, very helpful. Thank you. And then the second question I want to ask, so it sounds like storefront revenue in 2026 is supposed to have a meaningful step up. If possible, I was wondering if you could maybe size the range of storefront revenue you think is possible. And then, you know, if not, maybe you could give us some idea of what could drive upside to your internal expectations or, you know, on the other side, perhaps drive downside to those expectations.

Thanks. Sure. I'll start with the what, and then I'll answer with the why. So on the what side, I mean, I would say significant for us is going to be that it's 10% or thereabouts of total revenue. And without giving the exact number, because we haven't put numbers out for 2026 yet, we think that the storefront revenue associated with these developments that we've been talking about is going to be meaningful, meaning it'll be in that 10% range. And yes, I do think next year's revenue will be notably higher than this year's total revenue. As you get into Why do I feel like that? I think if you go back to my opening remarks about the strategic radar initiative, I cannot tell you how many meetings I've had in the last quarter since the last conference call face-to-face with these dibs that see what we're doing. They like the fact that we've done this tape out that we talked about. And, you know, even as of today, lots of calls and emails asking for when they can get their hands on this. And so when you start to see people pulling for the technology and you know the projects that are under development, public projects, right? The strategic defense system is going under a major modernization. That's all public knowledge. And if you throw into that this notion of hypersonics and Golden Dome, a lot of these programs are going to need some level from strategic radar down to radiation tolerant. And the part that we've got in the FAB now is designed to address those needs. So As we get it out, we start moving to these orders for dev kits. We start getting those out. Hopefully by the end of Q1, I think we're going to be a prime, a real prime spot to monetize that and start turning talk that I've had for two and a half years into actual revenue and bottom line contribution. But it's not just one entity here. We're talking about all the major dibs that we've been talking to. I think there's good demand for that. So that's why we think it's going to be meaningful for next year. Does that answer your question?

Thank you. Yes. Thank you very much. Great. You're welcome.

Our next question comes from Richard Shannon with Craig Hallam. You may proceed with your question.

Great. Thanks, Brian and Elias, for taking my questions. The quality of the audio here is pretty poor on my end, so hopefully you can hear me. Apologize if you can't hear. We can hear you just fine. Okay. Let's go. I guess at least one of us can. A lot of detail on the call here and some really interesting stuff going on here. Let me ask kind of a big picture, high-level question here with your new initiative on the GF12LP process or initiative here. I guess, how do we think about the opportunity for FPGAs versus ASICs? It would include your hard IP in here. And are the dynamics here for timing for each of these

markedly different than the other?

Well, I'd start by saying for 12LP, that is a very commonly used process by the defense industrial base. I think the heritage of that is that that was the most advanced process that Global Foundries had, and Global Foundries is US-owned and operated, and so if you wanted to have something that was manufactured onshore by a US company, that was sort of the most advanced you can get. Global has since come out with 12LP+, which is a more advanced version of 12LP. But if you think about what's involved in doing an ASIC or an SOC, you need lots of IP available, and you need lots of test data characterization on all that IP in order to feel comfortable to move forward with that on your ASIC. And in terms of the defense community, it's a very risk-averse community, as they should be. as they're designing a system. So there's a wealth of IP on 12LP that there is, it's today, it's known, it's understood characterization data, and the government, again, this is all publicly fundable, the government has been, you know, helping people do ASICs on 12LP. A lot of IP is available. There's government-funded multi-project wafers and all those things to encourage development on that node. So from that standpoint, I think you're going to see TOEFL P a lot. You've seen it in the past. You're going to see it in the future. So then the question for us is, okay, we have our IP on TOEFL P. Now we can build devices from that, or we could build, or we could license that for people doing their own ASICs. And I think we've already talked about IP licenses that we have on ASICs and you've heard timing on that. So people will start to be taping out those and going to production hopefully in the next few years. So there's a, a, There's a near-term license opportunity. There's a back-end royalty opportunity for us on that. And we definitely plan to monetize that to several million dollars a year. On the device side, that gets interesting because we've obviously taken our commercial total PIP and we've done a RadHeart implementation of that. So the goal behind that is to do this strategic RadHeart FBGA and having to take that out, if you fast forward to when we could do that actual product die for production on that, once that's out, that's going to be a significant step function increase in the revenue potential for us personally because devices of that nature are always going to have a much higher ASP than what a royalty contribution would be. So I think 12OP is critically important for us, and it's sort of a land and expand strategy on that now. We want to license it to as many people as we can. We want to have this strategic RFPGA capture. for revenue, and that's, I think, the basis of what could be hundreds of millions of dollars in revenue.

I don't know if I answered your question in its entirety. If I didn't, just tell me.

You did for the most part. I'm just trying to circle around this a bit here from a very high level. I'm going to ask another pretty high-level question here, Brian, which is, Comparing the opportunity you've now undergone with GFS 12LP, how do you compare the opportunity to what you've been doing with RadHard with the other founders you've announced with? I guess from a total perspective overall, I'll let you pick a timeframe, but how do you see the relative size of each of these opportunities for you?

By the other founders you're referring to, Skywater and Honeywell or somebody else?

Those are the ones, yes. Okay.

So I think without getting into programmatic details, I think that the 12LP opportunity for us is a larger opportunity because it has the strategic standard FPGA. It also has IP licensing as an option. And one of the nice things, and you know this, is that as you get smaller process technology, you get denser Transistors, you get more capability, you can stuff in a die, and there's going to be higher value to that. And we integrated that as far as where we're taking our eFPGA architecture, but the same is true at 12 nanometer and 12 LP. The more transistors and functionality we can stick on that die, the higher the value the part's going to be. And I think, again, the interesting part about 12 LP here is that we can get a lot of capability running on our FPGA 12 LP, and maybe somebody doesn't even need to do an ASIC now for 12 LP. That's huge. If we can start helping people address the needs of a mission without having to go off and do a custom ASIC, you're talking about saving a customer, the government, literally tens of millions of dollars in years of development cost and time. And that's the real benefit, I think, to getting our FPGA on 12 nanometer, given that it's strategic at heart and so capable of a node. Now, as you talk about those other foundries, those are older process geometries that they've talked about. There's going to be a difference in what you can do on the die. There's a difference in what you can do capability-wise. Not bad, just different. I think the bigger bucket of revenue for us is going to be what we're going to be able to do at 12 nanometer on these for the time being. Okay. And I don't want to get into more details on that just because that's a little too much programmatic information if I go further.

Yep, I get that. Just that high level here is very helpful to think about. Brian, thanks for that. You mentioned expecting orders for your new dev kits here, I think, by the end of this month and delivering those sometime next year. Can you give us a sense of how many dev kits and how many customers you expect to ship that to? And then what's kind of the design cycle once customers get that in hand in terms of their next steps?

So I'm not going to give numbers.

Probably not surprised to hear that. But it's going to be enough that it will be a significant revenue number, so not just a rounding number on the income statement. And we've, you know, Elias talked about the money that we spent in Q3 on that. We've intentionally bought enough DAI that we can... we can provide enough for these customers that want to test these things out, both in terms of DevKit and on just raw devices themselves on their own boards. Now, the way this works from an evaluation perspective, again, this is a very cautious and risk-averse community that we're talking about. They're going to want to do their own testing on these things, and that generally takes a couple quarters to go off and do all of your exercising of your design and the different environmental tests that need to need to be done on those devices. You've probably read the TRL levels, technology readiness level. You know, we want to get customers as quickly as possible to TRL 5. And TRL 5 is where they can actually say that they've taken the part and they've run it through the rigorous testing that's representative of the environment that they're going to operate in. And so we hope to be able to support our customers to get through that at some point through the middle of next year and then At that point, start intercepting actual programs of record with this and moving into pretty late stages of the design, hopefully, with them. And again, that's why time is so critical. That's why we took the leap of faith to do our own design and fund our own tape out, knowing that NPWs don't come along very often. And we wanted to make sure that we're on one that still gave us enough time to have the part come out, verify it, and get it into the hands of the dip so they can start playing with it.

in their own labs and not just trust our own data.

Okay, great perspective there, Brian. Last question, I'll jump out of line. A lot of irons in the fire that you have going on here, which is great to see here. And in quick logic, obviously, it's a fairly small company here. Seems like it might need a bit more support to a broad range of customers coming your way here very soon. How do we think about the know the spend levels we need to see next year you know whether it comes through uh um opex or the stuff that gets allocated to cogs here how do we think about where this could go if things go really well and you get a lot of attention a lot of a lot of activity these dev kits are sending out so i'll i'll start answering the last can can chime on this so from a from the engineering perspective and the go-to-market uh team perspective

You know, we obviously have identified certain critical hires. Some of them you can find on our website today. And these are all about getting the right resources to get the devices out into the hands of the div as soon as possible. And you can find that on our website. Engineering, field application engineering, and so on. As we move from test chip to actual product chip, there will be more expenses. There will be other things that need to be paid for. And I think that we have a good line of sight on what those are going to be. And it's not going to be outrageous for next year. I think it's going to be very mindful of where we are financially as a company and tied in with getting these customers on board with test trips so that any investments we do make is coming from the perspective of knowing what our customer wants, knowing the problem that our solution solves. And in some cases, even perhaps getting funding from customers to co-invest in these things so that they have skin in the game and it offsets the upfront cost for QuickLogic to get it to market.

Yep, correct. And in fact, Richard, if I may add, like, for example, we have three new hires we're looking for, all engineers. And as such, you know, OPEX is definitely headcount moderating. So I don't anticipate, even with all the additions that Brian is describing, probably we'll be looking at probably three and a half million of OPEX per quarter probably next year, but starting in Q2 or so.

I think for now we're okay with about under three.

Okay. That's great detail, guys. I will jump on. Thank you. Thanks, Richard.

Before our next question, as a reminder, if any analysts would like to ask a question, you may press star 1 on your telephone keypad to enter the queue. Our next question comes from Rick Neaton with Rivershore Investment Research. You may proceed with your question.

Thank you. Hi, Brian, and hi, Elias.

Hello, Rick.

I'd like to understand your Q4 guidance. Are you proposing an either-or situation where we're either going to have $3.5 million plus or minus or $6 million plus or minus? Is that what you're saying?

Yes, because there's an issue with timing, right? So if the order comes in, for example, to pay completed to six million it would come in late in the quarter and we may be able to recognize certain portions of that revenue uh but if it comes in and we're not able to deliver in that quarter let's just say it comes in on the day of our close of the day after it's definitely q1 at that point so it's it's almost like a timing issue rick and that's why we we were in we went to great pains to identify the difference between a $3.5 million revenue and a $6 million revenue, and really it's one order. And as such, it's all about timing. So it's very difficult to answer a question now to someone saying, okay, would you be able to recognize 100% of it? And the answer is clearly no, if it comes in in Q4. So that is why Brian and I agreed, if that's the case and we anticipate that order coming in, at least in Q4, Let's just hope it does.

We at least have the possibility of beating the high end of the range.

Okay. Thank you for that explanation. Sure. What do you forecast as your share count for 2025?

Well, 17 million, 90,000, 252,000 shares. That's outstanding right now. Okay.

One final question.

Yeah.

Yeah, yeah, no, that's fine. So that's your ending share count would be 17 million? Yes, sir. Okay. Three months ago, you described your expected revenue decline for 2025 with the adjective modest. And now your key four guidance suggests a 20 to 30% decline in annual revenue from 2024. What changed since August to cause what I would describe as a significant double-digit percentage-wise revenue decline?

Eric, that's the challenge with having large IP contract values when we're talking $3 million type ASPs for these. So I think in the call we mentioned one clearly is in 2026. So that goes from this year into next year. and then some other smaller ones that contribute to that, but again, when you have $3 million IP contracts, if they don't happen in the fiscal year, there's going to be a big change in percentage-wise from the revenue levels that we're at today. Once that becomes more of the norm and we get more of these higher-value contracts like we're talking about now, that starts to smooth out some of that lumpiness, but when we're at the stage where we are now, there's almost unavoidable if something goes out that's going to materially impact a percentage of that.

Okay. Thanks for that explanation, and thanks for having me on the call.

Thanks, Rick.

This now concludes our question and answer session. I would like to turn the floor back over to Brian Faith for closing comments.

I want to thank everybody for joining us today. Hopefully we'll connect with some of you at one of our upcoming events, including the Craig Hallam Alpha Select one-on-one conference in New York on November 18th, the Summit Conductor-focused annual New York Summit, also in New York on December 16th, or the annual Needham Growth Conference in early January 2026. Thank you, and have a good day.

Ladies and gentlemen, thank you for your participation. This does conclude today's teleconference. Please disconnect your lines and have a wonderful day.