QuickLogic Corporation

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everyone to the QuickLogic Corporation's third quarter fiscal 2025 earnings results conference call. As a reminder, today's call is being recorded for replay purposes through November 18th, 2025. I would now like to turn the conference over to Ms. Allison Ziegler of Darrow Associates. Ms. Ziegler, please go ahead.

Thank you, Vaughn, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited statements regarding our future profitability and cash flows, expectations regarding our future business, and statements regarding the timing, milestones, and payments related to our government contracts, statements regarding the use of the company's ATM program, and statements regarding our ability to successfully exit Sentinel. Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time to market of our new products, intense competition from competitors, our ability to hire and retain qualified personnel, changes in demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could cause disrupt supply or delivery of or demand of the company's products, and changes in tax rates and exposure to additional tax liabilities. For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please revert to the risk factors discussed in QlikLogic's most recently filed periodic reports with the SEC. QlikLogic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We've also posted an updated financial table on our IR webpage that provides current historical non-GAAP data. Please note, QuickLogic uses its website, public blogs, corporate Twitter account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR webpage shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our third quarter 2025 conference call. We have made very significant progress since our August conference call. Last quarter, I stated that we focused considerable engineering resources to accelerate storefront design wins for our strategic Rathart FPGA and expand our served available market to include very high density EFPGA hard IP designs targeting advanced fabrication nodes. I am proud to say our engineering team has executed beautifully, and we are realizing these goals. We expect to begin recognizing storefront revenue in early 2026, and that it will provide a meaningful contribution to total 2026 revenue. The interest from large defense industrial-based entities, or DIBs, in the SRH test chip we funded is notably higher than I anticipated. We have significantly expanded our ability to address the lucrative markets for very high-density discrete FPGAs and ASICs that require large blocks of eFPGA. New contracts and engagements are for much larger blocks of eFPGA and on advanced fabrication processes. The value contribution of eFPGA in customer designs has grown substantially. Our penetration in commercial market sectors is expanding, and with this progress, the rate of new contract closure is accelerating to the point that license revenue may surpass NRE revenue for the first time this quarter. We believe these trends will accelerate going forward. Before I get into the tangible data that support these points, I want to take a moment and provide some color for the revenue guidance Elias will share in his presentation. Based on our backlog and forecasts provided to us by our customers, we are targeting total revenue of $6 million for Q4. The majority of the contracts that support this outlook are already on the books or have been forecasted by customers to be awarded during the coming weeks. However, a contract valued at nearly $3 million for a commercial application targeting an advanced fabrication node has been forecasted by the customer to be awarded late in the quarter. If this contract is awarded on or very near the date forecasted, we will be able to recognize a large portion of that revenue in Q4, and with that, realize our $6 million objective. We have a very high level of confidence in winning this contract. But note that it could push into Q1 2026, and that would result in lower Q4 2025 total revenue. Due to this, Elias will present an unusually wide guidance range. And now let's walk through our accomplishments. In early August, we delivered design files to GlobalFoundries to fabricate our SRH FPGA test chip using its 12LP process. This test chip was designed to meet the requirements of certain large dibs that have programs in development today that are good candidates for this device. We expect delivery of test chips in early Q1 2026 and believe we will have our SRH dev kit ready for shipment to customers shortly thereafter. This initiative was financed by QuickLogic and is independent from our contract with the U.S. government. Our decision to invest the money and resources to develop this test chip was based on our belief that it is critical in our quest to secure strategic design wins and accelerate our storefront business model. Since our last earnings conference call, I have personally met with a number of the DIBs that worked with us through the development process, and I cannot emphasize enough the potential of our SRH storefront initiative. In prior meetings, all I had to show were PowerPoint presentations. And now with a test chip in fabrication, the level of enthusiasm is palpably higher. As a matter of fact, we already have commitments for SRH dev kit orders that we expect to receive by the end of this month. I see this as our first tangible step towards the hundreds of millions of dollars in potential storefront business we could win in the coming years. The importance of demonstrating our SRH FPGA test chip goes well beyond the storefront designs we believe it will enable us to secure. FPGA is the number one spend category for semiconductor devices by the Defense Industrial Base, and custom ASICs are a close second. Together, we believe these two categories make up roughly half of the DIB semiconductor TAM. We expect many of the new strategic designs that require various levels of radiation hardness We'll use either discrete FPGA devices that we can store front or eFPGA hard IP we can license in new ASIC designs. By delivering a discrete SRH FPGA test chip fabricated on the 12OP process, we are demonstrating the broader capability of our eFPGA hard IP for ASIC applications that will meet program requirements ranging from radiation tolerant to strategic rad hard. There are three very important points I want to highlight here. First, DIBs are already using Global Foundry's 12OP fabrication process for radiation tolerant and SRH ASICs. Second, government contracts require the use of onshore fabrication for strategic programs when devices are available. As it stands today, we will be the only source for strategic routered FPGAs and SRH eFPGA hard IP that is fabricated in the U.S. by a U.S. company. Third, in my meetings at large dibs, engineering managers have clearly stated that being able to design with our Aurora FPGA user tools for both our SRH discrete FPGAs and our eFPGA hard IP in ASIC designs is a huge plus. During our last conference call, I stated that Q3 would mark the low point for revenue recognition for our US government SRH FPGA contract this year. Funded by the current tranche, revenue recognition from the contract will rebound significantly in Q4. Beyond that, we anticipate an increase in quarterly revenue recognition in 2026 that will be funded by the next tranche. During our last conference call, I forecasted the award of a mid seven-figure contract from Adib during Q4 that targets Intel 18A. Unfortunately, there has been a delay in funding that pushes this contract into 2026. We are highly confident that we'll be awarded this contract, but at this juncture, our customer has limited visibility on the timing of funding. While we await funding for this seven-figure deal, It is worth noting that we have already been awarded multiple contracts by this strategic customer during 2025. We delivered customer-specific eFPGA hard IP for this customer's first Intel 18A test chip last April. We expect to receive our allocation of test chips from this contract during Q1 2026 for our internal verification and characterization. We were subsequently awarded a mid-six figure contract for a second Intel 18A test chip. We delivered customer-specific eFPGA hard IP for this test chip during Q3. In addition to these Intel 18A test chip contracts, during our last conference call, I announced this customer awarded us a contract for a 1 million LUT feasibility study that we are scheduled to deliver next week. We are anticipating a follow-on order in the coming weeks associated with this feasibility study that will enable the customer to tape out a very high-density Intel 18A proof-of-concept device during the second half of 2026. The architectural changes we implemented in this feasibility study can be leveraged across all advanced fabrication nodes, which we define as 12 nanometers and below. With these changes, we can now address the lucrative markets that require very high-density eFPGA blocks in ASIC design and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA hard IP and discrete devices, including our SRH FPGA, chiplets, and other storefront opportunities. We initiated our digital proof of concept chiplet program earlier this year as a strategy to accelerate our storefront chiplet initiative. Internally, we refer to this as POC. With the support of our large strategic partners, we have leveraged our existing EFPGA hard IP and readily available third party IP to move forward rapidly and with minimal investment. In line with the forecast I shared in our last conference call, we completed the initial phase of the digital FPGA chiplet POC where the eFPGA IP is connected to UCIE IP and the necessary interface logic for the IPs to communicate. This digital simulation of the POC is available now and can be further developed to meet different customer requirements. Together with our ecosystem partners, we are engaging with prospective customers in the defense, aerospace, industrial, and commercial markets. We plan to move forward with the next phases of the FPGA chiplet POC once external funding is committed. This phase will include incorporating additional IP, such as programmable GPIOs, AXI bus, DSPs, data converters, and interfaces such as PCI Express, to meet specific customer requirements. We are optimistic that our POC initiative will lead to storefront revenue in 2026. On October 2nd, we announced a new $1 million EFPGA hard IP contract for a high performance data center ASIC that will be fabricated on TSMC's 12 nanometer process. In this ASIC, our eFPGA hard IP will be the primary IP in the design. This contract is a great illustration of our success in several of the points I mentioned earlier. The need for larger blocks of eFPGA, the increasing value contribution of eFPGA in customer designs, winning contracts for designs targeting advanced fabrication processes, and our growing success in commercial market sectors. We will soon announce the expansion of our involvement with a DIB that specializes in cybersecurity for strategic and tactical weapon systems. This DIB designs secure system-on-chip processors that leverage the enhanced security that only eFPGA can provide. Running these processes and hardware is inherently more secure than software solutions. With eFPGA at the heart of the designs, the hardware can be altered to respond to new threats and updated algorithms. We are proud to have been chosen as a trusted supplier of EFPGA Hard IP for these designs. Last April, we announced an EFPGA Hard IP contract with a new defense industrial base customer valued at $1.1 million that will be fabricated on the GF12LP process. This application utilizes a large block of our eFPGA hard IP for critical functions, which is a trend we are seeing, particularly in designs targeting advanced fabrication nodes. With the cooperation of this Dib and its end customer, we are leveraging the large eFPGA core into a new seven-figure contract we expect to announce in the coming weeks. In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit will be compatible with common third-party development environments used by both TIBS and commercial customers. This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the 12LP test chip or our eFPGA hard IP in an ASIC. We anticipate having evaluation kits available in late 2026. With that, I will turn the call over to Elias for his presentation of financial data.