QuickLogic Corporation

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everybody to QuickLogic Corporation's fourth quarter and fiscal 2025 earning results conference call. As a reminder, today's call is being recorded. I would now like to turn the conference over to Ms. Allison Ziegler of Darrow Associates. Ms. Ziegler, please go ahead.

Thank you, Operator, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited to statements regarding our future profitability and cash flows, expectations regarding our future business and expected revenue growth, and statements regarding the timing, milestones, and payments related to our government contracts. Actual results may differ due to a variety of factors, including delays in the market acceptance of companies' new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenues, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low power, competitive pricing, and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters, and other business interruptions that could disrupt disrupt supply or delivery of or demand for the company's products and changes in tax rates and exposure to additional tax liabilities. For more detailed discussions of the risks, uncertainties, and assumptions that could result in those differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of publication of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR webpage that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate ex-account, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation FD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR webpage shortly after the conclusion of today's earnings call. I would now like to turn the call over to Brian. Go ahead, Brian.

Thank you, Alison. Good afternoon, everyone, and thank you all for joining our fourth quarter 2025 conference call. While certain contract delays over the course of the year resulted in much lower than expected 2025 revenue, we accomplished numerous tangible milestones that set the stage well for 2026 and beyond. Underscoring this is our forecast for nearly 50% sequential revenue growth in Q1. large contracts for very high-density EFPGA hard IP cores that are in late stages of negotiation, and the acceleration of our storefront business model, which we believe will drive a meaningful revenue contribution beginning in 2026. I'll take a few minutes now to update you on these and other accomplishments. In our February 18th press release, we announced QuickLogic was awarded a $13 million tranche for our ongoing contract with the U.S. government that was initiated in 2022. We will begin recognizing revenue from this tranche in Q1. In line with my comments during our last earnings conference call, this tranche funds increased quarterly revenue recognition relative to 2025. In parallel with our U.S. government contract, QuickLogic internally funded the development of an SRH FPGA test chip. Last August, we delivered design files to global foundries to fabricate our SRH FPGA test chip using its 12 LP process. This chip was designed to meet the specific requirements of certain large dibs that have programs in development today that are good candidates for this device. This investment positions us very well as the only source available today for a US fabricated FPGA that addresses the full spectrum of radiation hardness requirements. We received our SRH FPGA test chip samples earlier in Q1 and announced in a January 14th press release that we have received orders for our SRH FPGA Dev Kit that enables DIBs to evaluate the test chips. I view this as a strong demand signal and our first tangible step towards what I believe will be hundreds of millions of dollars in potential storefront business for our discrete SRH FPGA during the coming years. Beyond the discrete SRH FPGA market, we are leveraging this test chip to cast a much broader net. In addition to the applications that require strategic radiation hardness that are most likely to design using our storefront discrete SRH FPGA, There are many other applications with less rigorous radiation requirements that may prefer to integrate our SRH eFPGA hard IP in ASICs. DIBs are already using Global Foundry's 12OP fabrication process for various levels of radiation hardness in ASIC designs. By demonstrating our SRH FPGA test chip that is also fabricated on 12OP, We are positioning QuickLogic to address both discrete SRH FPGA requirements, as well as provide DIBs with the confidence they need to integrate our SRH eFPGA hard IP in future ASIC designs. In some cases, these DIBs may also elect to utilize our storefront services for their ASIC designs. The short story here is by leveraging the milestones accomplished in 2025, we believe we are very well positioned to successfully address both discrete and embedded FPGA designs across the full spectrum of radiation hardness requirements. And with the architectural enhancements we implemented last year that are extensible to 12LP, we have significantly expanded our SAM in these markets to include the lucrative applications for very high-density discrete and embedded FPGA. During our last conference call, I stated that a mid-seven-figure EFPGA hard IP contract leveraging Intel 18A was pushed into 2026 due to a delay in government funding. Based on our conversations with this DIB, we remain highly confident we will be awarded this contract once it is funded. While the timing of funding remains uncertain, Our discussions with this DIV have expanded to include the potential of QuickLogic providing storefront services for the customer-designed ASIC that will include our EFPGA hard IP. We expect that we will learn more about the potential expansion to storefront and the timing for this award in the coming months. During this funding delay and the discussions about expanding the scope of our participation, we have worked closely with this DIV on a variety of projects. Through these efforts, we have been awarded three smaller Intel 18A contracts that total well over $1 million, and a fourth is pending that will bring the total to nearly $2 million. The first two contracts were for Intel 18A test chips. We delivered IP for both in 2025 and expect to receive an allotment of test chips for our internal evaluation next quarter. The third contract was for a 1 million LUT feasibility study that we completed in Q4. A fourth contract, which we anticipate being awarded yet this quarter, leverages the architectural enhancements developed during the 1 million LUT study. In support of this contract, we will deliver HART-IP for a very large Intel 18A EFPGA core that customer plans to integrate into its ASIC that is targeted for tape-out during the second half of 2026. The architectural enhancements we developed in support of the One Million Let Study can be leveraged across all advanced fabrication nodes, which we define as 12 nanometers and smaller. These enhancements reduce power consumption, increase performance, and reduce the silicon area required for a given size block of our core FPGA technology. In industry terms, the enhancements materially improve our PPA. With these architectural enhancements in place, we can address the lucrative markets that require very high-density eFPGA cores in ASIC designs and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA hard IP and discrete devices, including our SRH FPGA, chiplets, and other storefront opportunities. In addition to these DIB contracts, we are working closely with a large commercial customer on a new Intel 18A contract valued at several million dollars. We originally expected this contract would be awarded in late Q4. However, the customer decided to expand the size of the eFPGA core in their ASIC to provide greater programmable flexibility. While this is a beneficial trend for QuickLogic, it has delayed the contract award. We are currently forecasting this contract will be awarded during Q2. During our November 2025 conference call, I stated that we would soon announce the expansion of our involvement with a DIB that specializes in cybersecurity for strategic and tactical weapon systems. On December 8th, we issued a press release announcing Idaho Scientific selected our EFPGA hard IP for forward-leaning hardware-based cryptographic solutions designed to address mobile IoT infrastructure and defense systems. Idaho Scientific has a rich history in leveraging FPGA technology to deliver robust security systems that can adapt quickly to changing external threats without the vulnerabilities that are inherent in software-based solutions. By integrating our eFPGA hard IP into its secure system-on-chip processors, It can further enhance its cryptographic security and address new markets much more quickly and with lower risks and lower costs. Last April, we announced an EFPGA hard IP contract with a new defense industrial-based customer valued at $1.1 million that will be fabricated on the GF12LP process. This application utilizes a large block of our EFPGA hard IP for critical functions. which is a trend we are seeing in designs targeting advanced fabrication notes. With the cooperation of this DIB and its end customer, we are leveraging the large EFPGA core into a new seven-figure contract that we expect to announce this year. However, due to the fact this contract involves multiple parties, it is taking longer than we expected to finalize. Based on current forecasts, we anticipate the contract award later this quarter. In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit, which is currently scheduled for late 2026, will be compatible with common third-party development environments used by both DIBs and commercial customers. This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the discrete FPGA or our eFPGA hard IP in an ASIC. In parallel with these efforts, we're exploring the potential to leverage the FPGA as a chiplet that is co-packaged with one of our partner's microcontrollers. We are already seeing interest from some of our partners on this concept. We completed the initial phase of our digital proof of concept chiplet program in 2025 as a strategy to accelerate our storefront chiplet initiative. Internally, we refer to this as POC. With the support of our large strategic partners, we leveraged our existing eFPGA HART IP and readily available third-party IP to move this program forward rapidly and with minimal investment. With ongoing debates regarding the communications and protocol layers of chiplet interfaces, this POC and our decades of experience in FPGA bridging positions us well as a potential solution to move chiplet designs forward to satisfy what appears to be significant pent-up demand. We were invited to present a paper on our POC at the recent Chiplet Summit and at the Intel Foundry's Partners presentation at the upcoming GoMAC, together with Cadence and Trusted Summit Conductor Solutions. The net takeaway from our presentation at the Chiplet Summit supports our optimism that chiplets will build traction in 2026. The primary hurdles today are interoperability gaps, and we believe a storefront FPGA chiplet is the logical solution for a programmable bridge. Earlier this year, Epson gave us permission to share its case study that supports our claims that using FPGA technology to process algorithms lowers power consumption without sacrificing programmability relative to processing and software. We published the results in a blog post on January 13th. Epson's SOC was originally architected to run workloads entirely in software. But as demand for more features and real-time responsiveness grew, power consumption became a limiting factor. Epson's engineering team recognized that moving compute-intensive functions into dedicated hardware could deliver significant efficiency gains. But the hardware solution would need to be capable of adapting to changes in algorithms. This meant the only practical solution would be an eFPGA core integrated inside the SOC. By using our proprietary Astralis eFPGA IP generator, we were able to quickly deliver a customized hard IP core specifically designed to the SOC application that targeted TSMC's E12N fabrication technology. Adding to our challenge was the fact that this would be our first eFPGA hard IP for E12N. From design handoff to silicon validation, the IP integrated cleanly into Epson's SOC without the need for respins or late-stage design changes. Epson was able to boot, configure, and validate the eFPGA subsystem immediately, accelerating its schedule and reducing risk. After final testing, Epson confirmed the resulting design reduced overall power consumption by 50%. This makes a huge difference for battery-powered systems. Given our success in this design, we believe we are very well positioned for future opportunities with Epson, as well as other companies with similar requirements. As I'm sure you noticed in our 8K, we took a large impairment charge on Sensible. This is due to the standard accounting practice to impair the value of an asset held for sale for a year or longer. During the last year, we have discussed the divestiture of Sensible with microcontroller companies, and in one case, those discussions advanced to due diligence. but were concluded without an agreement. We are in discussions today with a large company where sensible software potentially presents high value for new AI and drone projects. We cannot provide assurance that this or other discussions will result in a transaction. With that, I will turn the call over to Elias for his presentation of financial data.