QuickLogic Corporation

Ladies and gentlemen, good afternoon. At this time, I would like to welcome everybody to QuickLogic Corporation's first quarter fiscal 2026 earnings results conference call. As a reminder, today's call is being recorded for replay purposes. I would now like to turn the conference over to Ms. Allison Ziegler of Darrow Associates. Ms. Ziegler, you may proceed.

Thank you, Sherry, and thanks to all of you for joining us. Our speakers today are Brian Faith, President and Chief Executive Officer, and Elias Nader, Senior Vice President and Chief Financial Officer. As a reminder, some of the comments QuickLogic makes today are forward-looking statements that involve risks and uncertainties, including but not limited to statements regarding our future profitability and cash flows, expectations regarding our future business, and statements regarding the timing, milestones, and payments related to our government contracts, statements regarding the expected magnitude of potential contracts, and statements regarding the expected adoption rates and our orders by our customers. Actual results may differ due to a variety of factors, including delays in the market acceptance of the company's new products, the ability to convert design opportunities into customer revenue, our ability to replace revenue from end-of-life products, the level and timing of customer design activity, the market acceptance of our customers' products, the risk that new orders may not result in future revenue, our ability to introduce and produce new products based on advanced wafer technology on a timely basis, our ability to adequately market the low-power competitive pricing and short time to market of our new products, intense competition by competitors, our ability to hire and retain qualified personnel, changes in product demand or supply, general economic conditions, political events, international trade disputes, natural disasters and other business interruptions that could disrupt supply or delivery of or demand for the company's products, and changes in tax rates and exposure to additional tax liabilities. For more detailed discussions of the risks, uncertainties, and assumptions that could result in these differences, please refer to the risk factors discussed in QuickLogic's most recently filed periodic reports with the SEC. QuickLogic assumes no obligation to update any forward-looking statements or information which speak as of the respective dates of any new information or future events. In today's call, we will be reporting non-GAAP financial measures. You may refer to the earnings release we issued today for a detailed reconciliation of our GAAP to non-GAAP results and other financial statements. We have also posted an updated financial table on our IR webpage that provides current and historical non-GAAP data. Please note, QuickLogic uses its website, the company blog, corporate Twitter accounts, Facebook page, and LinkedIn page as channels of distribution of information about its business. Such information may be deemed material information, and QuickLogic may use these channels to comply with its disclosure obligations under Regulation SD. A copy of the prepared remarks made on today's call will be posted on QuickLogic's IR webpage shortly after the conclusion of today's earnings call. I'd now like to turn the call over to Brian. Go ahead, Brian.

Thank you Allison. Good afternoon everyone and thank you all for joining our first quarter 2026 conference call. Since our last conference call, we have made significant progress toward our goal of delivering 50 to 100% year over year revenue growth in 2026. With this, we continue to expect storefront and our new Rad Pro FPGA will contribute to our anticipated revenue growth and second half profitability. As we announced in an April 9th press release, we introduced and demonstrated our new RADPRO FPGA and Development Kit at the Hardened Electronics and Radiation Technology, or HART, conference last month. HART is a highly specialized conference where attendees must show proof of U.S. citizenship and their affiliation with a company or academia that is certified through the Joint Certification Programs. RADPRO is our trademarked brand for radiation-hardened FPGAs. The test chip we demonstrated at the HART conference with our RADPRO dev kit was internally funded and is independent of our U.S. government contract. These test chips were fabricated on the Global Foundries 12LP process, which is the same process used by many DIBs for radiation-hardened ASICs. This means that in addition to successfully demonstrating our new discrete RADPRO FPGA, We have also illustrated our capability to support requirements for eFPGA and radiation-hardened ASICs and SOCs fabricated on the Global Foundries 12LP process. Our demonstrations and meetings at heart with leading DIBs went very well, and we have since shipped multiple RadPro dev kits. These shipments will provide a low six-figure contribution to our Q2 revenue. While we expect it will take until the end of 2026 for DIBs to fully evaluate our new RadPro FPGA, we have already signed an MOU with one DIB to accelerate the mutual evaluation of a potential RadPro chiplet application. In addition to the progress we've made with our RadPro FPGA, in a March 17th press release, we announced our fourth contract targeting Intel 18A technology. While these initial contracts have been smaller, their total value is now nearly $2 million, and together they are the framework for the larger contracts we expect to book later this year. The first two contracts were for Intel 18A test chips. We anticipate receiving our test chip allocation from the first contract later this quarter. We believe the data we gather from our evaluation of these test chips will enhance our ability to win new production contracts. The third contract was for a 1 million LUT feasibility study, which led us to implement some notable architectural enhancements that we can leverage across all advanced fabrication nodes. With these architectural enhancements in place, we can address the lucrative markets that require very high-density eFPGA cores in ASIC designs and very high-density discrete FPGAs. This significantly expands our SAM for eFPGA hard IP and discrete devices, including chiplets and a variety of storefront opportunities. The fourth and most recent contract leverages the architectural enhancements that were developed during the 1 million left feasibility study. In support of this contract, we will deliver hard IP for a very large Intel 18A eFPGA core in support of our customer's ASIC design. The test ship for this ASIC design is targeted for tape out during the second half of 2026. We anticipate a fifth mid six-figure contract from this customer during the second half of 2026 that further extends our work on very high density architecture. While the timing of funding remains uncertain, our discussions with this DIB have expanded to include the potential of QuickLogic providing storefront services for a customer designed ASIC that will include our EFPGA HART IP. We expect to learn more about the potential expansion to SOAR Front Services and the timing of this possible award in the coming months. In addition to these DIB contracts, we are working closely with a large commercial customer contract based on Intel 18A valued at several million dollars. In our last conference call, I said that I expected this contract would be awarded in late Q2. However, the customer is evaluating an expansion in the size and function of the eFPGA core in their ASIC to provide greater programmable flexibility. While this is a beneficial trend for QuickLogic, we are now forecasting this contract to be awarded during Q3. On December 8th, we issued a press release announcing Idaho Scientific selected our eFPGA hard IP for forward-leaning, hardware-based cryptographic solutions designed to address mobile IoT infrastructure and defense systems applications. We are continuing to support the integration of our HART IP into the tape out that is anticipated next year. Idaho Scientific has a rich history in leveraging FPGA technology to deliver robust security systems that can adapt quickly to changing external threats without the vulnerabilities that are inherent in software-based solutions. By integrating our EFPGA hard IP into its secure system on a chip processors, Idaho Scientific can further enhance its cryptographic security and address new markets much more quickly with lower risks and lower costs. Since our last conference call, Idaho Scientific has been fully integrated with General Dynamics mission systems. We believe this integration may lead to new opportunities for QuickLogic. Last year, we announced an EFPGA HART IP contract with a new defense industrial base customer valued at $1.1 million that will be fabricated on the GF12LP process. This application utilizes a large block of our EFPGA HART IP for critical functions, which is a trend we are seeing in designs targeting advanced fabrication nodes. With the cooperation of this DIV and its end customer, We have leveraged the large EFPGA core to win a new seven-figure contract that was finalized last week and will contribute to Q2 revenue. The delay of this award is why our Q1 revenue was below the midpoint of our guidance. In the scope of this new contract, we will be provided with test chips that we will incorporate in an evaluation kit. The evaluation kit, which is currently scheduled for late 2026, will be compatible with common third-party development environments used by both DIBs and commercial customers. This enables these customers to accelerate system-level evaluations and designs that can use either a storefront version of the discrete FPGA or our eFPGA hard IP in an ASIC. In parallel with these efforts, we're exploring the potential to leverage the FPGA from this contract as a storefront chiplet. We are already seeing interest from some of our partners on this concept. Due largely to the strategic initiatives we launched in 2025, we believe we are building meaningful traction in the chiplet markets. We are currently working on numerous proposals at various stages that include direct U.S. government, DIB, and commercial applications. These proposals include opportunities targeting several fabrication processes including Global Foundries 12OP and Intel 18A. Last year, the commercial chiplet ecosystem was mired in debate regarding the communications and protocol layers. In response, we introduced the first phase of our digital proof-of-concept chiplet program as a strategy to move forward prior to customer commitments, and with that, accelerate our storefront chiplet initiatives. Internally, we refer to this as POC, With the support of our large strategic partners, we leveraged our existing EFPGA hard IP and readily available third-party IP to move this program forward rapidly and with minimal investment. We presented a paper on the POC at the Chiplet Summit in mid-February and gave a presentation with Intel Foundry at an event at the Government Microcircuit Applications and Critical Technology, or GOMAC, tech conference in March. As a reminder, QuickLogic is a member of the Intel Foundry Accelerator Ecosystem Alliance Program, participating in the Chiplet, IP, and USMAG alliances. In our last conference call, I stated that the net takeaway from our presentation at the Chiplet Summit supports our optimism that chiplets will build traction in 2026. This opinion was bolstered at the GoMAC Tech Conference. The primary hurdles today are interoperability gaps, and we believe a storefront FPGA chiplet is the logical solution for a programmable bridge. With that, I will turn the call over to Elias for his presentation of financial data.