Synopsys, Inc.

Ladies and gentlemen, welcome to the Synopsis Earnings Conference Call for the first quarter fiscal year 2025. At this time, all participants are in a listen-only mode. Later, we will conduct a question and answer session. If you would like to ask a question at that time, please press star 1 on your telephone keypad. To remove yourself from the queue, it is, again, star 1. If you should require assistance during the calls, please press star zero and an operator will assist you. Today's call will last one hour. As a reminder, today's call is being recorded. At this time, I would like to turn the conference over to Trey Campbell, Senior Vice President, Investor Relations. Please go ahead.

Good afternoon, everyone. With us today are Sassine Ghazi, President and CEO of Synopsys, and Sheila Glazer, CFO. Before we begin, I'd like to remind everyone that during the course of this conference call, Synopsys will discuss forecasts, targets, and other forward-looking statements regarding the company and its financial results. While these statements represent our best current judgment about future results and performance as of today, our actual results are subject to many risks and uncertainties that could cause actual results to differ materially from what we expect. In addition to any risks that we highlight during this call, important factors that may affect our future results are described in our most recent SEC reports and today's earnings press release. In addition, we will refer to certain non-GAAP financial measures during the discussion. Reconciliations to their most directly comparable GAAP financial measures and supplemental financial information can be found in the earnings press release, financial supplement, and 8 that we released earlier today. All of these items, plus the recent investor presentation, are available on our website at www.synopsys.com. In addition, the prepared remarks will be posted on our website at the conclusion of the call. With that, I'll turn the call over to Saseen. Good afternoon.

We had a solid start to 2025, exceeding the midpoint of our Q1 revenue guidance and delivering non-GAAP EPS above our guidance range. As we outlined in December, Q1 revenue was down 4% year over year, and non-GAAP EPS was down 10% as we had one less work week in Q125 versus Q124. Let me take a few minutes to share some business highlights, and then Sheila will discuss the financials in more detail. From an end market perspective, AI and HPC remained robust in the first quarter, while industrial, automotive, and consumer electronics remained challenged. Despite the stale of two markets, along with headwinds in China as we anticipated, synopsis opportunity is tied to R&D and underpinned by the megatrends of AI, silicon proliferation, and software-defined systems. These trends are increasing design complexity and cost, while driving greater compute and energy demands. New design paradigms are essential to address these challenges, and Synopsys is racing to deliver. I had the privilege to meet with semi and automotive customers at CES in January, who all expressed their strong belief in the strategy we are driving. They underscored the pressing need for solutions to design, validate, and optimize intelligent products virtually from silicon to systems. Our pending acquisition of ANSYS will pave the way for new AI-powered design solutions that fuse electronics and physics, giving R&D teams the tools they need to ignite their future innovation. In January, the European Commission approved our pending pro-competitive acquisition of ANSYS, and the UK CMA provisionally accepted our remedies toward the phase one approval. As previously communicated, the US HSR Act waiting period has expired, and we're making strong progress with other regulatory agencies, including China. Customers overwhelmingly support this transaction, and we continue to anticipate closing in the first half of 2025. Moving to business highlights. In Q1, design automation revenue was up 4% year over year with one less week of revenue versus the prior Q1, while design activity remained strong. Synopsys is the leader in hardware-assisted verification, or HAV, solutions, and this month we strengthened our position, expanding our industry-leading HAV portfolio to include new HAPS 200 prototyping systems and new Zebu 200 emulation systems with up to 2x better performance versus our prior generation. AMD, ARM, NVIDIA, and Sci-5 are among a number of customers who are deploying our new prototyping and emulation technologies, and we were honored by their participation in our recent launch. Last year, we had our best year ever in hardware, and we expect another year of strong performance based on the enthusiasm for our newly expanded Synopsys HAV portfolio, which provides the unmatched performance and flexibility our customers require to prototype, emulate, and verify ever more integrated, complex, and software-defined systems. Turning to EDA software, where we are seeing strong design activity at advanced nodes with two nanometer projects accelerating rapidly. Fusion Compiler is the industry-leading platform for advanced node digital design implementation, and this quarter we saw a U.S. hyperscaler tape out a 2-nanometer test chip exclusively using a Synopsys design flow. Additionally, at 2-nanometer, Fusion Compiler was the platform of choice for a US HPC CPU tape out and an Asian mobile customers two nanometer SOC. Moving to sign off technologies where we offer the industries essential trusted solutions to close out timing, signal integrity, power and variation aware analysis. Headlining our portfolio is prime time. which is used by virtually all key advanced node customers. Customers are reporting significant productivity improvements with the most recent prime time release, with one customer achieving 30% faster turnaround time with multi-core scaling. Our IC validator product family is delivering tremendous value in physical verification sign-off. and recent product improvements have unleashed even greater turnaround time improvements for customers. Leading-edge customers are achieving greater than 2x turnaround time for full-chip physical verification sign-off at 3 nanometer and below, enabling design teams to finish more sign-off runs within the budget cycle time to improve the quality of results. Before moving out of sign-off, a few points on StarRC, which is the industry-leading tool for extraction on advanced process nodes. To date, we've seen all of our major CPU and GPU customers on TSMC N3 and Intel 18A using StarRC for sign-off extraction, with the key differentiation being the accuracy of results and tool performance relative to competition. The massive AI infrastructure build-out that's currently underway paves the way for AI transformation across all industries, including our own. AI is fueling chip innovation and the AI-driven EDA capabilities we pioneered from reinforcement learning to generative AI capabilities are delivering significant productivity gains and cementing our leadership position. But we're only at the beginning. While customers are realizing compelling value from our initial AI-driven optimization engines, these enhanced capabilities have not yet dramatically altered the underlying design flow for a chip. We see a paradigm shift coming with agentic AI, where engineers can task autonomous agents with executing complex workflows. We believe this will be massive value and productivity unlock for our industry, which we'll talk more about at our Synopsys user group conference in March. But first, AI business highlights from this quarter. In Q1, We continue to drive Synopsys.ai adoption across our tools in design implementation, verification, test, and analog. In verification, or VSO.ai, we saw a large US memory company begin deployment of VSO.ai to find corner case bugs, realize a 2x improvement in hardware utilization, while an Asian hyperscale customer achieved a 4x turnaround time improvement with VSO.AI on its HPC design, significantly improving hardware utilization and outperforming the competition. Our analog migration tool, ASO.AI, continues to build a strong pipeline of customer opportunities, and in Q1, delivered a significant competitive displacement at the leading aerospace company. We also continue to expand our generative AI offerings for customers. We recently added script generation capabilities to the co-pilots for Fusion Compiler and Primetime, and early customer results are demonstrating 30% average productivity improvements for designers. Additionally, Synopsys.ai generative formal verification capability in Verdi is delivering up to a 35% productivity boost in early engagements with key partners. Onto Design IP. In line with our expectations, revenue was down 17% year over year versus a record setting prior year compare. While IP revenue can fluctuate quarter to quarter, the opportunity set for IP continues to expand, particularly as AI customers accelerate protocol transitions and look for creative ways to drive enhanced performance per watt. This quarter, we launched the industry's first Ultra Accelerator Link or UAL and Ultra Ethernet IP solutions to connect massive AI accelerator clusters, addressing the industry need for open standard solutions to scale AI accelerator infrastructure. We also continue to optimize our foundation IP libraries to deliver unparalleled AI performance. One, high-performance AI customer used our memory and logic libraries to deliver breakthrough LLM performance at 5 nanometer. Across our interface IP portfolio, AI continues to push protocols forward at breakneck pace as customers drive for additional performance per watt. This quarter, We captured several key design wins, including a cutting-edge PCIe 7.0 design with an AI infrastructure chip provider, and we secured a 224-gig Ethernet win with a major ecosystem player. We also secured a 112-gig SerDes and PCIE 6.0 agreement with a leading European telecommunications equipment provider and an interface IP development deal for a leading auto OEMs advanced two nanometer design. Our IP development for the Foundry ecosystem is a mission critical ingredient for the industry and in Q1, we announced silicon success for PCIe 4.0 Phi IP on Samsung's SS8 process used in auto, mobile, networking, and storage applications. Also in Q1, we demonstrated silicon success for our one-time programmable, non-volatile memory IP. This technology enables secure storage for encryption keys, product configuration, and SRAM repair information and is now available in TSMC N4P, N5, N6, and N7 processes. Moving to mobile and consumer markets where end market demand is challenging, but design activity continues as customers ready a next wave of innovative products. A leading Asian automotive supplier adopted Synopsys interface, processor, and foundation IP due to our long track record of delivering high quality IP. Also in Q1, We closed the design win, including PCIe 4.0, MIPI, and USB with a leading mobile provider for an ARM-based application processor. UFS, or Universal Flash Storage, is a key technology in these verticals. And we closed a UFS design with a key company driving AI PCs this quarter. We also continue to see strong demand for the advanced UFS protocol in mobile to support LLM storage for GenAI use cases. A few closing comments before we transition to Sheila's remarks. We have a very resilient business model and our solutions are mission critical to our customers' innovation. We have strong momentum across the business bolstered by secular growth tailwinds, including AI. The application of AI for EDA and engineering more broadly is just beginning, which we'll discuss in more detail at Snug in March. Finally, thank you to our employees, customers, and partners for a strong start to 2025. We are excited to continue our partnership journey with you through the year. With that, I'll turn it over to Sheila.